diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-10-23 16:05:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:35 +0000 |
| commit | bb7f4c7a4f3a076ba3e52fea9228e4a064316128 (patch) | |
| tree | 42e496c03922bcd91d01b5772d1d0f660088d4ce /src/soc/mediatek/mt8183/include | |
| parent | 0f5d7b9daf3b2c7a2991c62580c9db9c3e8ac953 (diff) | |
mediatek/mt8183: Correct MPU ctrl register address
Remove unused members in emi_mpu_regs and sdram_params. Change
mpu_ctrl_d to array so the offset (0x804) for D1 is corrected.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/29251
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_register.h | 21 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/emi.h | 2 |
2 files changed, 4 insertions, 19 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index ac76e51ff5..c88eaa0725 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -936,25 +936,12 @@ check_member(chn_emi_regs, chn_emi_shf0, 0x0710); struct emi_mpu_regs { uint32_t mpu_ctrl; - uint32_t mpu_dbg; - uint32_t rsvd_2[62]; - uint32_t mpu_sa0; - uint32_t rsvd_3[63]; - uint32_t mpu_ea0; - uint32_t rsvd_4[63]; - uint32_t mpu_apc0; - uint32_t rsvd_5[319]; - uint32_t mpu_ctrl_d0; - uint32_t rsvd_6[63]; - uint32_t rg_mask_d0; + uint32_t rsvd[511]; + uint32_t mpu_ctrl_d[16]; }; -check_member(emi_mpu_regs, mpu_dbg, 0x0004); -check_member(emi_mpu_regs, mpu_sa0, 0x0100); -check_member(emi_mpu_regs, mpu_ea0, 0x0200); -check_member(emi_mpu_regs, mpu_apc0, 0x0300); -check_member(emi_mpu_regs, mpu_ctrl_d0, 0x0800); -check_member(emi_mpu_regs, rg_mask_d0, 0x0900); +check_member(emi_mpu_regs, mpu_ctrl, 0x0000); +check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); enum { TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12, diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index c3c8e81cfa..22331ae42b 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -25,8 +25,6 @@ struct sdram_params { u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; - s8 clk_delay; - s8 dqs_delay[CHANNEL_MAX]; u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; |