diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-04-20 19:33:28 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:50:45 +0000 |
| commit | 062646670fe0b750e1c8398321c21054e30ff054 (patch) | |
| tree | a347a7d8a8e648ad0bd0ab8258020311f93b2c7b /src/soc/mediatek/mt8183/include | |
| parent | efaf1b32ba1eb69b8968de7e0f67e8fc66fca0d5 (diff) | |
soc/mediatek/mt8183: Set CA and DQ vref range to correct value
The CA vref should alway select range[1]. But in fast calibration flow,
we missed the range selection and caused the CA vref to use the range[0] value.
The DQ vref should select correct range that corresponds to current frequency,
that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps
to select range[0].
Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf',
used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels.
MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%,
MR14 range[0] and range[1] values same as MR12.
BUG=b:153614919
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 07b50d6585..66433602c5 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -74,12 +74,12 @@ enum { DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16, - SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), - SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6), SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2), SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6), + SELPH_DQS0_3200 = _SELPH_DQS_BITS(0x3, 0x3), + SELPH_DQS1_3200 = _SELPH_DQS_BITS(0x5, 0x2), SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3), SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6), }; |