diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-07-14 15:46:08 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-20 07:24:04 +0000 |
| commit | c157ee97d422f3afa406926b5f9a291a8478532f (patch) | |
| tree | 22dcfb02b124d0f0507fc1b2d016ae86c3d284d5 /src/soc/mediatek/mt8183/include | |
| parent | 7378015b740713f7ecd3ee53715154de1411541a (diff) | |
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps,
2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386
BRANCH=none
TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 21 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_register.h | 7 |
2 files changed, 6 insertions, 22 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index a2ff08d1c3..1ce5f67470 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -50,16 +50,6 @@ enum { }; enum { - TX_DQ_DQS_MOVE_DQ_ONLY = 0, - TX_DQ_DQS_MOVE_DQM_ONLY, - TX_DQ_DQS_MOVE_DQ_DQM -}; - -enum { - MAX_CA_FINE_TUNE_DELAY = 63, - MAX_CS_FINE_TUNE_DELAY = 63, - MAX_CLK_FINE_TUNE_DELAY = 31, - CATRAINING_NUM = 6, PASS_RANGE_NA = 0x7fff }; @@ -76,10 +66,8 @@ enum { enum { DQS_GW_COARSE_STEP = 1, - DQS_GW_FINE_START = 0, DQS_GW_FINE_END = 32, DQS_GW_FINE_STEP = 4, - DQS_GW_FREQ_DIV = 4, RX_DQS_CTL_LOOP = 8, RX_DLY_DQSIENSTB_LOOP = 32 }; @@ -102,10 +90,6 @@ enum { DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16, - DQS_DELAY_2T = 3, - DQS_DELAY_0P5T = 4, - DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5, - SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), @@ -124,9 +108,10 @@ u8 get_freq_fsq(u8 freq_group); void dramc_init(const struct sdram_params *params, u8 freq_group); void dramc_sw_impedance_save_reg(u8 freq_group); void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); -void dramc_apply_config_before_calibration(void); +void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(void); -void dramc_calibrate_all_channels(const struct sdram_params *params); +void dramc_calibrate_all_channels(const struct sdram_params *pams, + u8 freq_group); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 8bed1baef5..fb8d7d78f9 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -945,15 +945,12 @@ enum { }; enum { + MISC_STATUSA_SREF_STATE = 16, MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000, }; enum { - SPCMDRESP_RDDQC_RESPONSE_SHIFT = 7, -}; - -enum { DDRCONF0_DM4TO1MODE_SHIFT = 22, DDRCONF0_RDATRST_SHIFT = 0, }; @@ -974,6 +971,8 @@ enum { }; enum { + MRS_MPCRK_SHIFT = 28, + MRS_MPCRK_MASK = 0x30000000, MRS_MRSRK_SHIFT = 24, MRS_MRSRK_MASK = 0x03000000, MRS_MRSMA_SHIFT = 8, |