diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-09-26 17:39:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-11 08:57:16 +0000 |
| commit | 2b5067b2c70bf0e0a995b6e33485a8ac15268cbc (patch) | |
| tree | 75ba50d1d2efe7767dd36cdd47d09c5de958f1f2 /src/soc/mediatek/mt8183/include | |
| parent | 0655761b67d515fbe44ec5b31c3e58167d5f2b4e (diff) | |
mediatek/mt8183: Add DDR driver of tx rx window perbit cal part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I4434897864993e254e1362416316470083351493
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 24 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_register.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/emi.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/memlayout.ld | 2 |
4 files changed, 5 insertions, 25 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 3fb8c25d47..7b3215840d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -27,17 +27,11 @@ #define dramc_dbg(_x_...) #endif -#define ENABLE 1 -#define DISABLE 0 - #define DATLAT_TAP_NUMBER 32 -#define MAX_CMP_CPT_WAIT_LOOP 10000 -#define TIME_OUT_CNT 100 - #define DRAMC_BROADCAST_ON 0x1f #define DRAMC_BROADCAST_OFF 0x0 -#define MAX_BACKUP_REG_CNT 32 +#define TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP 64 #define IMP_LP4X_TERM_VREF_SEL 0x1b #define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a @@ -50,11 +44,6 @@ enum dram_te_op { }; enum { - DBI_OFF = 0, - DBI_ON -}; - -enum { FSP_0 = 0, FSP_1, FSP_MAX @@ -75,17 +64,6 @@ enum { }; enum { - GATING_OFF = 0, - GATING_ON = 1 -}; - -enum { - CKE_FIXOFF = 0, - CKE_FIXON, - CKE_DYNAMIC -}; - -enum { GATING_PATTERN_NUM = 0x23, GATING_GOLDEND_DQSCNT = 0x4646 }; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 5d79b4949b..2487504a28 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -1145,7 +1145,7 @@ enum { }; enum { - SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT = 7, + SHU1_BX_DQ7_R_DMDQMDBI_SHIFT = 7, SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT = 0, SHU1_BX_DQ7_R_DMRANKRXDVS_MASK = 0x0000000f, }; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 22331ae42b..81e3d91daa 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -33,6 +33,8 @@ struct sdram_params { u16 delay_cell_unit; }; +extern const u8 phy_mapping[CHANNEL_MAX][16]; + int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index f148eed519..2a6d42de63 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SECTIONS SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) - OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 92K) + OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 110K) BOOTBLOCK(0x00227000, 89K) VERSTAGE(0x0023E000, 114K) SRAM_L2C_END(0x00280000) |