soc/mediatek/mt8183: Do TX tracking for DRAM DVFS feature

The TX window will offset to edge during DVFS switch, which may cause
TX data transmission error and random kernel crash. Therefore, use the
standard dqsosc (DQS Oscillator) for TX window tracking.

BUG=b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

2 files changed, 157 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
index 54f009e9f0..59eb6dd3d4 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
@@ -29,6 +29,7 @@
 #endif
 
 #define DATLAT_TAP_NUMBER 32
+#define HW_REG_SHUFFLE_MAX  4
 
 #define DRAMC_BROADCAST_ON 0x1f
 #define DRAMC_BROADCAST_OFF 0x0
@@ -38,6 +39,7 @@
 #define IMP_DRVP_LP4X_UNTERM_VREF_SEL	0x1a
 #define IMP_DRVN_LP4X_UNTERM_VREF_SEL	0x16
 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL	0x1a
+#define MR23_DEFAULT_VALUE		0x3f
 
 enum dram_te_op {
 	TE_OP_WRITE_READ_CHECK = 0,
@@ -114,5 +116,8 @@ void dramc_hw_gating_onoff(u8 chn, bool onoff);
 void dramc_enable_phy_dcm(bool bEn);
 void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);
 void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off);
+u32 get_shu_freq(u8 shu);
+void dramc_hw_dqsosc(u8 chn);
+void dramc_dqs_precalculation_preset(void);
 
 #endif /* _DRAMC_PI_API_MT8183_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
index b3ee6af4c7..8c1f9efa4d 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
@@ -627,12 +627,18 @@ check_member(emi_mpu_regs, mpu_ctrl, 0x0000);
 check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);
 
 DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)
+DEFINE_BIT(SPCMDRESP_DQSOSCEN_RESPONSE, 10)
+DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1)
 DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)
+DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0)
 
 DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22)
 DEFINE_BIT(DDRCONF0_RDATRST, 0)
 DEFINE_BIT(PERFCTL0_RWOFOEN, 4)
 
+DEFINE_BIT(RKCFG_DQSOSC2RK, 11)
+DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26)
+
 DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3)
 DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0)
 
@@ -655,16 +661,19 @@ DEFINE_BITFIELD(MRS_MRSBA, 23, 21)
 DEFINE_BITFIELD(MRS_MRSMA, 20, 8)
 DEFINE_BITFIELD(MRS_MRSOP, 7, 0)
 
+DEFINE_BIT(SPCMD_DQSOSCENEN, 10)
 DEFINE_BIT(SPCMD_DQSGCNTRST, 9)
 DEFINE_BIT(SPCMD_DQSGCNTEN, 8)
 DEFINE_BIT(SPCMD_ZQLATEN, 6)
 DEFINE_BIT(SPCMD_RDDQCEN, 7)
 DEFINE_BIT(SPCMD_ZQCEN, 4)
+DEFINE_BIT(SPCMD_MRREN, 1)
 DEFINE_BIT(SPCMD_MRWEN, 0)
 
 DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11)
 
 DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)
+DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0)
 
 DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1)
 
@@ -727,7 +736,39 @@ DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24)
 DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20)
 
 DEFINE_BIT(SHU1_WODT_DBIWR, 29)
+DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30)
+DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18)
 DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0)
+DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29)
+DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30)
+DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30)
+
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15)
+DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20)
+DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3)
+DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8)
+
+DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16)
+DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18)
+DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19)
+
+DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24)
+DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14)
+DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0)
+DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0)
+DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7)
+DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24)
+DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31)
+
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0)
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12)
+DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16)
+DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20)
+DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0)
 
 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
@@ -736,6 +777,8 @@ DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4)
 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0)
+DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0)
+DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16)
 
 DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
 DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
@@ -769,6 +812,115 @@ DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24)
 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8)
 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0)
 
+/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */
+DEFINE_BIT(PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22)
+DEFINE_BIT(PRE_TDQSCK1_TDQSCK_REG_DVFS, 25)
+DEFINE_BIT(PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK2) */
+DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, 7, 0)
+DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, 15, 8)
+DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, 23, 16)
+DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, 31, 24)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK3) */
+DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, 7, 0)
+DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, 15, 8)
+DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, 23, 16)
+DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, 31, 24)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK4) */
+DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, 7, 0)
+DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, 15, 8)
+DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, 23, 16)
+DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, 31, 24)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0) */
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1, 30, 28)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED, 26, 24)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1, 22, 20)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED, 18, 16)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED, 10, 8)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1) */
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1, 30, 28)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED, 26, 24)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1, 22, 20)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED, 18, 16)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1, 14, 12)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED, 10, 8)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1, 6, 4)
+DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED, 2, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, 25, 19)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0, 18, 13)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN) */
+DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS3IEN, 30, 24)
+DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS2IEN, 22, 16)
+DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS1IEN, 14, 8)
+DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS0IEN, 6, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK3) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0, 17, 12)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0, 11, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK2) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK4) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0, 25, 19)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0, 18, 13)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK6) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0, 17, 12)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0, 11, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK5) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK7) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0, 25, 19)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0, 18, 13)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK9) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0, 17, 12)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0, 11, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK8) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK10) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0, 25, 19)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0, 18, 13)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK12) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0, 17, 12)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0, 11, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0)
+
+/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK11) */
+DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6)
+DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0)
+
 struct dramc_channel_regs {
 	union {
 		struct dramc_ddrphy_ao_regs phy;