soc/mediatek/mt8183: Use cached calibration result for faster bootup

Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.

Bootup time of DRAM partial calibration:
 - 1,349,385 usecs with low frequency
 -   924,698 usecs with middle frequency
 - 1,270,089 usecs with high frequency
3,544,172 usecs in total.

Bootup time of DRAM fast calibration:
 - 216,663 usecs with low frequency
 - 328,220 usecs with middle frequency
 - 322,612 usecs with high frequency
867,495 usecs in total.

BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 45 insertions, 3 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h
index 15889eeca4..ab21bc7e12 100644
--- a/src/soc/mediatek/mt8183/include/soc/emi.h
+++ b/src/soc/mediatek/mt8183/include/soc/emi.h
@@ -20,10 +20,49 @@
 #include <types.h>
 #include <soc/dramc_common_mt8183.h>
 
+enum DRAMC_PARAM_SOURCE {
+	DRAMC_PARAM_SOURCE_SDRAM_INVALID = 0,
+	DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	DRAMC_PARAM_SOURCE_FLASH,
+};
+
 struct sdram_params {
+	u16 source;	/* DRAMC_PARAM_SOURCE */
+	u16 frequency;
 	u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
-	u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
+
+	/* DUTY */
+	s8 duty_clk_delay[CHANNEL_MAX];
+	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER];
+
+	/* CBT */
 	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
+
+	/* Gating */
+	u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+	u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+	u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+
+	/* TX perbit */
+	u8 tx_vref[CHANNEL_MAX][RANK_MAX];
+	u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+	u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
+	u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+	u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+	u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+
+	/* datlat */
+	u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
+
+	/* RX perbit */
+	u8 rx_vref[CHANNEL_MAX];
+	s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+	u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+
 	u32 emi_cona_val;
 	u32 emi_conh_val;
 	u32 emi_conf_val;
@@ -46,7 +85,7 @@ int complex_mem_test(u8 *start, unsigned int len);
 size_t sdram_size(void);
 const struct sdram_params *get_sdram_config(void);
 void enable_emi_dcm(void);
-void mt_set_emi(const struct sdram_params *params);
-void mt_mem_init(const struct sdram_params *params);
+void mt_set_emi(const struct sdram_params *freq_params);
+void mt_mem_init(const struct sdram_params *freq_params);
 
 #endif /* SOC_MEDIATEK_MT8183_EMI_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
index 73c880afbf..82e404f790 100644
--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
@@ -24,6 +24,8 @@
  */
 #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
 #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
+#define DRAM_INIT_CODE(addr, size) \
+	REGION(dram_init_code, addr, size, 4)
 
 SECTIONS
 {
@@ -42,6 +44,7 @@ SECTIONS
 	SRAM_L2C_START(0x00200000)
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K)
 	BOOTBLOCK(0x00230000, 64K)
+	DRAM_INIT_CODE(0x00240000, 256K)
 	SRAM_L2C_END(0x00280000)
 
 	DRAM_START(0x40000000)