diff options
| author | Ran Bi <ran.bi@mediatek.com> | 2019-04-17 15:43:14 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-06 18:20:46 +0000 |
| commit | fcfa35670a191d2313324fb313bac237e7a3d0c6 (patch) | |
| tree | f99a682c23ff9dfd5b4eac5847058f3f1cc4e95e /src/soc/mediatek/mt8183/include | |
| parent | e458bcd099b5fd97c39a424bcc47e99818942487 (diff) | |
mediatek/mt8183: Enable RTC eosc calibration feature to save power
When system shuts down, RTC enable eosc calibration feature to save
power. Then coreboot RTC driver needs to call rtc_enable_dcxo function
at every boot to switch RTC clock source to dcxo.
BUG=b:128467245
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/rtc.h | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fec41..841a202519 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -100,18 +100,25 @@ enum { }; enum { - RTC_EMBCK_SRC_SEL = 1 << 8, - RTC_EMBCK_SEL_MODE = 3 << 6, - RTC_XOSC32_ENB = 1 << 5, - RTC_REG_XOSC32_ENB = 1 << 15 + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_REG_XOSC32_ENB = 1U << 15 }; enum { - RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, - RTC_LPD_OPT_EOSC_LPD = 1 << 13, - RTC_LPD_OPT_XOSC_LPD = 2 << 13, - RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, - RTC_LPD_OPT_MASK = 3 << 13 + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13 }; /* PMIC TOP Register Definition */ |