mediatek/mt8183: Calibrate RTC eosc clock

Calibrate RTC eosc clock which will be used when RTC goes into
low power state.

BUG=b:133872611
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 58 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 1f6f06a568..5a61208eee 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -128,6 +128,9 @@ enum {
 
 /* PMIC TOP Register Definition */
 enum {
+	PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
+	PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
+	PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
 	PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
 	PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
 	PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
@@ -136,6 +139,11 @@ enum {
 	PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
 };
 
+enum {
+	PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
+	PMIC_RG_FQMTR_CK_PDN_SHIFT = 11
+};
+
 /* PMIC DCXO Register Definition */
 enum {
 	PMIC_RG_DCXO_CW00 = 0x0788,
@@ -155,6 +163,56 @@ enum {
 	PMIC_RG_TOP_TMA_KEY = 0x03A8
 };
 
+/* PMIC Frequency Meter Definition */
+enum {
+	PMIC_RG_FQMTR_CKSEL	= 0x0118,
+	PMIC_RG_FQMTR_RST	= 0x013E,
+	PMIC_RG_FQMTR_CON0	= 0x0514,
+	PMIC_RG_FQMTR_WINSET	= 0x0516,
+	PMIC_RG_FQMTR_DATA	= 0x0518,
+
+	FQMTR_TIMEOUT_US	= 8000
+};
+
+enum {
+	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
+	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
+	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
+	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
+	PMIC_FQMTR_FIX_CLK_SMPS_CK	= 4U << 0,
+	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
+	PMIC_FQMTR_FIX_CLK_PMU_75K	= 6U << 0,
+	PMIC_FQMTR_CKSEL_MASK		= 7U << 0
+};
+
+enum {
+	PMIC_FQMTR_RST_SHIFT = 8
+};
+
+enum {
+	PMIC_FQMTR_CON0_XOSC32_CK	= 0U << 0,
+	PMIC_FQMTR_CON0_DCXO_F32K_CK	= 1U << 0,
+	PMIC_FQMTR_CON0_EOSC32_CK	= 2U << 0,
+	PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
+	PMIC_FQMTR_CON0_FQM26M_CK	= 4U << 0,
+	PMIC_FQMTR_CON0_FQM32k_CK	= 5U << 0,
+	PMIC_FQMTR_CON0_TEST_CK		= 6U << 0,
+	PMIC_FQMTR_CON0_TCKSEL_MASK	= 7U << 0,
+	PMIC_FQMTR_CON0_BUSY		= 1U << 3,
+	PMIC_FQMTR_CON0_DCXO26M_EN	= 1U << 4,
+	PMIC_FQMTR_CON0_FQMTR_EN	= 1U << 15
+};
+
+enum {
+	RTC_FQMTR_LOW_BASE = 794 - 2,
+	RTC_FQMTR_HIGH_BASE = 794 + 2
+};
+
+enum {
+	RTC_XOSCCALI_START = 0x00,
+	RTC_XOSCCALI_END = 0x1f
+};
+
 /* external API */
 void rtc_bbpu_power_on(void);
 void rtc_osc_init(void);