soc/mediatek/mt8183: Enable CA perbit mechanism

LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 105 insertions, 4 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
index b5ae253cdf..c630b5aa90 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
@@ -29,6 +29,7 @@ enum dram_odt_type {
 };
 
 enum {
+	CA_NUM_LP4 = 6,
 	DQ_DATA_WIDTH = 16,
 	DQS_BIT_NUMBER = 8,
 	DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER)
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h
index e35e4f5421..f925162e4a 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h
@@ -10,7 +10,7 @@
 
 enum {
 	DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b,
-	DRAMC_PARAM_HEADER_VERSION = 3,
+	DRAMC_PARAM_HEADER_VERSION = 4,
 };
 
 enum DRAMC_PARAM_STATUS_CODES {
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
index 437ed3db2d..a0937d01c6 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
@@ -27,6 +27,7 @@
 #define IMP_DRVN_LP4X_UNTERM_VREF_SEL	0x16
 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL	0x1a
 #define MR23_DEFAULT_VALUE		0x3f
+#define CA_TRAINING_NUM			10
 
 enum dram_te_op {
 	TE_OP_WRITE_READ_CHECK = 0,
@@ -42,6 +43,17 @@ enum {
 	GATING_GOLDEND_DQSCNT = 0x4646
 };
 
+enum cke_type {
+	CKE_FIXOFF = 0,
+	CKE_FIXON,
+	CKE_DYNAMIC
+};
+
+typedef enum {
+	CBT_LOW_FREQ = 0,
+	CBT_HIGH_FREQ,
+} cbt_freq;
+
 enum {
 	IMPCAL_STAGE_DRVP = 0x1,
 	IMPCAL_STAGE_DRVN,
@@ -98,14 +110,15 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option,
 void dramc_apply_config_before_calibration(u8 freq_group);
 void dramc_apply_config_after_calibration(const struct mr_value *mr);
 int dramc_calibrate_all_channels(const struct sdram_params *pams,
-				 u8 freq_group, const struct mr_value *mr);
+				 u8 freq_group, struct mr_value *mr);
 void dramc_hw_gating_onoff(u8 chn, bool onoff);
 void dramc_enable_phy_dcm(u8 chn, bool bEn);
 void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);
-void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off);
 u32 get_shu_freq(u8 shu);
 void dramc_hw_dqsosc(u8 chn);
 void dramc_dqs_precalculation_preset(void);
 void get_dram_info_after_cal(u8 *density);
+void set_mrr_pinmux_mapping(void);
+void dramc_cke_fix_onoff(enum cke_type option, u8 chn);
 
 #endif /* _DRAMC_PI_API_MT8183_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
index 1e1448b923..99005a19a6 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
@@ -623,8 +623,9 @@ DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22)
 DEFINE_BIT(DDRCONF0_RDATRST, 0)
 DEFINE_BIT(PERFCTL0_RWOFOEN, 4)
 
+DEFINE_BITFIELD(RKCFG_TXRANK, 1, 0)
+DEFINE_BIT(RKCFG_TXRANKFIX, 3)
 DEFINE_BIT(RKCFG_DQSOSC2RK, 11)
-DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26)
 
 DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3)
 DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0)
@@ -797,6 +798,7 @@ DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8)
 
 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24)
 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8)
+DEFINE_BITFIELD(SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 13, 8)
 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0)
 
 /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */
@@ -908,6 +910,90 @@ DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0)
 DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6)
 DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0)
 
+/* DRAMC_REG_MRR_BIT_MUX1 */
+DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24)
+DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16)
+DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8)
+DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0)
+
+/* DRAMC_REG_SHU_SELPH_CA7 */
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20)
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16)
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12)
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8)
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4)
+DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0)
+
+/* DRAMC_REG_MRR_BIT_MUX2 */
+DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8)
+DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0)
+
+/* DDRPHY_SHU1_R0_CA_CMD0 */
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, 23, 20)
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, 19, 16)
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, 15, 12)
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, 11, 8)
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, 7, 4)
+DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, 3, 0)
+
+/* DDRPHY_PLL2 */
+DEFINE_BIT(PLL2_RG_RCLRPLL_EN, 31)
+
+/* DDRPHY_PLL1 */
+DEFINE_BIT(PLL1_RG_RPHYPLL_EN, 31)
+
+/* DRAMC_REG_PADCTRL */
+DEFINE_BITFIELD(PADCTRL_FIXDQIEN, 19, 16)
+
+/* SPM_POWER_ON_VAL0 */
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 22)
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 25)
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 16)
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 11)
+DEFINE_BITFIELD(SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL_PCM, 31, 30)
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 27)
+DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 26)
+
+/* SPM_POWER_ON_VAL1 */
+DEFINE_BIT(SPM_POWER_ON_VAL1_SC_DR_SHORT_QUEUE_PCM, 31)
+
+/* SPM_DRAMC_DPY_CLK_SW_CON */
+DEFINE_BITFIELD(DRAMC_DPY_CLK_SW_CON_SC_DMDRAMCSHU_ACK, 25, 24)
+
+/* DRAMC_REG_DRAMC_PD_CTRL */
+DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0)
+DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30)
+DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26)
+
+/* DRAMC_REG_WRITE_LEV */
+DEFINE_BIT(WRITE_LEV_DQS_WLEV, 7)
+DEFINE_BITFIELD(WRITE_LEV_DQSBX_G, 11, 8)
+DEFINE_BITFIELD(WRITE_LEV_DQS_SEL, 19, 16)
+DEFINE_BITFIELD(WRITE_LEV_DMVREFCA, 27, 20)
+DEFINE_BIT(WRITE_LEV_WRITE_LEVEL_EN, 0)
+DEFINE_BIT(WRITE_LEV_BYTEMODECBTEN, 3)
+
+/* DRAMC_REG_STBCAL */
+DEFINE_BIT(STBCAL_DQSIENCG_NORMAL_EN, 29)
+
+/* DDRPHY_B0_DQ5 */
+DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17)
+
+/* DDRPHY_B1_DQ5 */
+DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17)
+
+/* DDRPHY_B0_DQ3 */
+DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1)
+
+/* DDRPHY_B1_DQ3 */
+DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1)
+
+/* DDRPHY_CA_CMD5  */
+DEFINE_BIT(CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN, 17)
+
+/* DDRPHY_CA_CMD3  */
+DEFINE_BIT(CA_CMD3_RG_RX_ARCMD_SMT_EN, 1)
+
 struct dramc_channel_regs {
 	union {
 		struct dramc_ddrphy_ao_regs phy;
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h
index cf794dee89..6931d5bb81 100644
--- a/src/soc/mediatek/mt8183/include/soc/emi.h
+++ b/src/soc/mediatek/mt8183/include/soc/emi.h
@@ -27,6 +27,7 @@ struct sdram_params {
 	u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
 	u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
 	u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER];
 
 	/* Gating */
 	u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];