diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-10-23 16:05:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:35 +0000 |
| commit | bb7f4c7a4f3a076ba3e52fea9228e4a064316128 (patch) | |
| tree | 42e496c03922bcd91d01b5772d1d0f660088d4ce /src/soc/mediatek/mt8183/emi.c | |
| parent | 0f5d7b9daf3b2c7a2991c62580c9db9c3e8ac953 (diff) | |
mediatek/mt8183: Correct MPU ctrl register address
Remove unused members in emi_mpu_regs and sdram_params. Change
mpu_ctrl_d to array so the offset (0x804) for D1 is corrected.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/29251
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/emi.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/emi.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 78e0b28ec7..286c87253a 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -54,7 +54,7 @@ static u64 get_ch_rank_size(u8 chn, u8 rank) row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) + ((emi_cona >> (12 + chn * 16 + rank * 2)) & 0x03)) + 13; - /* data width (bytes) * 8 banks */ + /* Data width (bytes) * 8 banks */ return ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); } @@ -80,7 +80,7 @@ void dramc_get_rank_size(u64 *dram_rank_size) else ch_rank0_size = (ch0_rank0_size * 256 << 20); - /* dual rank enable */ + /* Dual rank enable */ if ((emi_cona & (1 << 17)) != 0) { if (ch0_rank1_size == 0) ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1); @@ -115,7 +115,7 @@ size_t sdram_size(void) for (int i = 0; i < RANK_MAX; i++) { dram_size += rank_size[i]; - dramc_show("rank%d size:0x%llx\n", i, rank_size[i]); + dramc_show("Rank%d size:0x%llx\n", i, rank_size[i]); } return dram_size; @@ -126,7 +126,7 @@ static void set_rank_info_to_conf(const struct sdram_params *params) u8 u4value = 0; /* CONA 17th bit 0: Disable dual rank mode - * 1: Enable dual rank mode */ + 1: Enable dual rank mode */ u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1; clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12); } @@ -249,8 +249,8 @@ static void emi_init2(const struct sdram_params *params) { emi_esl_setting2(); - setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4); - setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4); + setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); + setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); |