diff options
author | Yu-Ping Wu <yupingso@google.com> | 2019-10-03 09:45:16 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-24 07:51:51 +0000 |
commit | 85ca1fe4e6311bd12b89fc1cfd28bf07896d3117 (patch) | |
tree | fb97e9db48b3682b721af13448e423f3781441e6 /src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | |
parent | c5568a145fdd0c9ccf9dff7e3bfb9ffc44328a3f (diff) |
soc/mediatek/mt8183: Improve DRAM calibration logs
- Add macro dramc_err.
- Some log levels are changed.
- Some messages are improved for readability.
BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot
Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_calibration_api.c')
-rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0c45ea05fa..ab92a7c943 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1036,14 +1036,14 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, } for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], - best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], - best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -1189,7 +1189,7 @@ static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val); break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1302,7 +1302,7 @@ static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, *end = *begin + 64; break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1429,7 +1429,7 @@ static bool dramk_calc_best_vref(enum CAL_TYPE type, u8 vref, break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } @@ -1997,7 +1997,7 @@ static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, *test_passed = (sum != 0); if (!*test_passed) { - dramc_show("DRAM memory test failed\n"); + dramc_err("DRAM memory test failed\n"); return 0; } @@ -2118,8 +2118,8 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group) u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K: freq=%d, ch=%d, rank=%d\n", - freq_group, chn, rk); + dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", + freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams, fast_calib); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); |