diff options
| author | Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> | 2020-12-04 17:00:56 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:29:17 +0000 |
| commit | 5ff588dbc10bbf69f140cebf3a584f1ed563b1c5 (patch) | |
| tree | fd72c40c3efe8160bb36f8c70ef14531c949de01 /src/soc/mediatek/mt8183/dramc_pi_basic_api.c | |
| parent | f296273692785da1bc88df8d28d955f8d79390e7 (diff) | |
soc/mediatek/mt8183: Support byte mode and single rank DDR
1. Add emi setting to support byte mode and single rank ddr sample
2. Modify initial setting for DDR with different architecture
BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_basic_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 4a884b1976..d992371fac 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -347,9 +347,9 @@ static void dramc_phy_low_power_enable(u8 chn) (chn == CHANNEL_A) ? 0xba000 : 0x3a000); } -static void dramc_dummy_read_for_tracking_enable(u8 chn) +static void dramc_dummy_read_for_tracking_enable(u8 chn, u32 rk_num) { - setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16); + setbits32(&ch[chn].ao.dummy_rd, rk_num << 16); for (size_t r = 0; r < 2; r++) for (size_t i = 0; i < 4; i++) @@ -403,7 +403,7 @@ static void dramc_enable_dramc_dcm(void) } } -void dramc_runtime_config(void) +void dramc_runtime_config(u32 rk_num) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) clrbits32(&ch[chn].ao.refctrl0, 0x1 << 29); @@ -412,7 +412,7 @@ void dramc_runtime_config(void) setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - dramc_hw_dqsosc(chn); + dramc_hw_dqsosc(chn, rk_num); /* RX_TRACKING: ON */ dramc_rx_input_delay_tracking(chn); @@ -426,7 +426,7 @@ void dramc_runtime_config(void) (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); /* DUMMY_READ_FOR_TRACKING: ON */ - dramc_dummy_read_for_tracking_enable(chn); + dramc_dummy_read_for_tracking_enable(chn, rk_num); /* ZQCS_ENABLE_LP4: ON */ clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); |