diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-08 17:40:55 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-06 03:02:17 +0000 |
| commit | cac990f18668a979397d706361d2690fe1d7a220 (patch) | |
| tree | fe54e336ea14170a297d62165b834c8037e29514 /src/soc/mediatek/mt8183/dramc_pi_basic_api.c | |
| parent | 8aca8da2eaf2f58ad7dd956323cbbb0589e7c157 (diff) | |
soc/mediatek/mt8183: Add missing register settings for channels
Some DRAM control settings need to apply to all channels,
so add those missing settings.
Also fix a typo (0x1 < 0) to (0x1 << 0).
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_basic_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index aa156f74f6..4a884b1976 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -47,10 +47,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + } impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -91,7 +93,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -150,9 +152,6 @@ void dramc_sw_impedance_save_reg(u8 freq_group, sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -202,7 +201,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group, SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); } static void transfer_pll_to_spm_control(void) |