diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-04-20 19:33:28 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:50:45 +0000 |
| commit | 062646670fe0b750e1c8398321c21054e30ff054 (patch) | |
| tree | a347a7d8a8e648ad0bd0ab8258020311f93b2c7b /src/soc/mediatek/mt8183/dramc_init_setting.c | |
| parent | efaf1b32ba1eb69b8968de7e0f67e8fc66fca0d5 (diff) | |
soc/mediatek/mt8183: Set CA and DQ vref range to correct value
The CA vref should alway select range[1]. But in fast calibration flow,
we missed the range selection and caused the CA vref to use the range[0] value.
The DQ vref should select correct range that corresponds to current frequency,
that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps
to select range[0].
Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf',
used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels.
MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%,
MR14 range[0] and range[1] values same as MR12.
BUG=b:153614919
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_init_setting.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_init_setting.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 2440814f1d..6f7ae37743 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -1218,8 +1218,8 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200); for (size_t rank = 0; rank < 2; rank++) { clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], @@ -1373,6 +1373,9 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); + /* The default dramc init settings were tuned at frequency of 3200Mbps. + For other frequencies uses dramc_setting_DDRxxx() to overwrite + the default settings. */ switch (freq_group) { case LP4X_DDR1600: dramc_setting_DDR1600(); |