diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/mediatek/mt8183/ddp.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/ddp.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/ddp.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 3c2b0fd662..50d6caf776 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -42,7 +42,7 @@ static void disp_config_main_path_mutex(void) static void ovl_bgclr_in_sel(u32 idx) { - setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); } static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, @@ -74,10 +74,10 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | - CG_CON1_DISP_DSI0_INTERFACE); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); } void mtk_ddp_init(void) |