mediatek: Refactor PMIC wrapper code among similar SoCs

Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot

Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

7 files changed, 222 insertions, 552 deletions

diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index e125e03146..b2a5ebdd33 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -27,7 +27,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 endif
 
-bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c
+bootblock-y += ../common/gpio.c gpio.c gpio_init.c
+bootblock-y +=  ../common/pmic_wrap.c pmic_wrap.c mt6391.c
 bootblock-y += ../common/wdt.c
 bootblock-y += ../common/mmu_operations.c mmu_operations.c
 
@@ -56,7 +57,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 romstage-y += ../common/cbmem.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/spi.c spi.c
-romstage-y += pmic_wrap.c mt6391.c
+romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
 romstage-y += memory.c
 romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
 romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
@@ -72,7 +73,7 @@ ramstage-y += soc.c ../common/mtcmos.c
 ramstage-y += ../common/timer.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
-ramstage-y += pmic_wrap.c mt6391.c i2c.c
+ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c
 ramstage-y += mt6311.c
 ramstage-y += da9212.c
 ramstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c
index 872ed6cf11..072edee872 100644
--- a/src/soc/mediatek/mt8173/emi.c
+++ b/src/soc/mediatek/mt8173/emi.c
@@ -24,6 +24,7 @@
 #include <soc/dramc_register.h>
 #include <soc/dramc_pi_api.h>
 #include <soc/mt6391.h>
+#include <soc/pmic_wrap.h>
 #include <soc/pll.h>
 #include <soc/infracfg.h>
 #include <soc/pericfg.h>
@@ -33,15 +34,15 @@ struct emi_regs *emi_regs = (void *)EMI_BASE;
 static void dram_vcore_adjust(void)
 {
 	/* options: Vcore_HV_LPPDR3/Vcore_NV_LPPDR3/Vcore_LV_LPPDR3 */
-	mt6391_write(PMIC_RG_VCORE_CON9, Vcore_NV_LPPDR3, 0x7F, 0);
-	mt6391_write(PMIC_RG_VCORE_CON10, Vcore_NV_LPPDR3, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCORE_CON9, Vcore_NV_LPPDR3, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCORE_CON10, Vcore_NV_LPPDR3, 0x7F, 0);
 }
 
 static void dram_vmem_adjust(void)
 {
 	/* options: Vmem_HV_LPPDR3/Vmem_NV_LPPDR3/Vmem_LV_LPPDR3 */
-	mt6391_write(PMIC_RG_VDRM_CON9, Vmem_NV_LPDDR3, 0x7F, 0);
-	mt6391_write(PMIC_RG_VDRM_CON10, Vmem_NV_LPDDR3, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VDRM_CON9, Vmem_NV_LPDDR3, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VDRM_CON10, Vmem_NV_LPDDR3, 0x7F, 0);
 }
 
 static void emi_init(const struct mt8173_sdram_params *sdram_params)
diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h
index 3091d06ed3..65b2f7ce8c 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6391.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h
@@ -294,8 +294,6 @@ enum ldo_voltage {
  */
 int mt6391_configure_ca53_voltage(int uv);
 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel);
-u32 mt6391_read(u16 reg, u32 mask, u32 shift);
-void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift);
 void mt6391_enable_reset_when_ap_resets(void);
 void mt6391_init(void);
 
diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
index 6807b13cbe..3687a2992d 100644
--- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
+++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
@@ -17,15 +17,10 @@
 #define SOC_MEDIATEK_MT8173_PMIC_WRAP_H
 
 #include <soc/addressmap.h>
+#include <soc/pmic_wrap_common.h>
 #include <types.h>
 
-/* external API */
-s32 pwrap_read(u16 adr, u16 *rdata);
-s32 pwrap_write(u16 adr, u16 wdata);
-s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
-s32 pwrap_init(void);
-
-static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
+static struct mt8173_pwrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
 
 enum {
 	WACS2 = 1 << 4
@@ -44,12 +39,6 @@ enum {
 	PMIC_TOP_CKCON3      = PMIC_BASE + 0x01D4
 };
 
-/* timeout setting */
-enum {
-	TIMEOUT_READ_US        = 255,
-	TIMEOUT_WAIT_IDLE_US   = 255
-};
-
 /* PMIC_WRAP registers */
 struct mt8173_pwrap_regs {
 	u32 mux_sel;
@@ -136,36 +125,6 @@ struct mt8173_pwrap_regs {
 
 check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
 
-enum {
-	RDATA_WACS_RDATA_SHIFT = 0,
-	RDATA_WACS_FSM_SHIFT   = 16,
-	RDATA_WACS_REQ_SHIFT   = 19,
-	RDATA_SYNC_IDLE_SHIFT,
-	RDATA_INIT_DONE_SHIFT,
-	RDATA_SYS_IDLE_SHIFT,
-};
-
-enum {
-	RDATA_WACS_RDATA_MASK = 0xffff,
-	RDATA_WACS_FSM_MASK   = 0x7,
-	RDATA_WACS_REQ_MASK   = 0x1,
-	RDATA_SYNC_IDLE_MASK  = 0x1,
-	RDATA_INIT_DONE_MASK  = 0x1,
-	RDATA_SYS_IDLE_MASK   = 0x1,
-};
-
-/* WACS_FSM */
-enum {
-	WACS_FSM_IDLE     = 0x00,
-	WACS_FSM_REQ      = 0x02,
-	WACS_FSM_WFDLE    = 0x04, /* wait for dle, wait for read data done */
-	WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag
-				   * clearing */
-	WACS_INIT_DONE    = 0x01,
-	WACS_SYNC_IDLE    = 0x01,
-	WACS_SYNC_BUSY    = 0x00
-};
-
 /* dewrapper regsister */
 enum {
 	DEW_EVENT_OUT_EN   = DEW_BASE + 0x0,
@@ -195,57 +154,10 @@ enum {
 	DEW_CIPHER_IV5     = DEW_BASE + 0x30
 };
 
-/* dewrapper defaule value */
-enum {
-	DEFAULT_VALUE_READ_TEST  = 0x5aa5,
-	WRITE_TEST_VALUE         = 0xa55a
-};
-
 enum pmic_regck {
 	REG_CLOCK_18MHZ,
 	REG_CLOCK_26MHZ,
 	REG_CLOCK_SAFE_MODE
 };
 
-/* manual commnd */
-enum {
-	OP_WR    = 0x1,
-	OP_CSH   = 0x0,
-	OP_CSL   = 0x1,
-	OP_OUTS  = 0x8,
-	OP_OUTD  = 0x9,
-	OP_INS   = 0xC,
-	OP_IND   = 0xD
-};
-
-/* error information flag */
-enum {
-	E_PWR_INVALID_ARG             = 1,
-	E_PWR_INVALID_RW              = 2,
-	E_PWR_INVALID_ADDR            = 3,
-	E_PWR_INVALID_WDAT            = 4,
-	E_PWR_INVALID_OP_MANUAL       = 5,
-	E_PWR_NOT_IDLE_STATE          = 6,
-	E_PWR_NOT_INIT_DONE           = 7,
-	E_PWR_NOT_INIT_DONE_READ      = 8,
-	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
-	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
-	E_PWR_INIT_SIDLY_FAIL         = 11,
-	E_PWR_RESET_TIMEOUT           = 12,
-	E_PWR_TIMEOUT                 = 13,
-	E_PWR_INIT_RESET_SPI          = 20,
-	E_PWR_INIT_SIDLY              = 21,
-	E_PWR_INIT_REG_CLOCK          = 22,
-	E_PWR_INIT_ENABLE_PMIC        = 23,
-	E_PWR_INIT_DIO                = 24,
-	E_PWR_INIT_CIPHER             = 25,
-	E_PWR_INIT_WRITE_TEST         = 26,
-	E_PWR_INIT_ENABLE_CRC         = 27,
-	E_PWR_INIT_ENABLE_DEWRAP      = 28,
-	E_PWR_INIT_ENABLE_EVENT       = 29,
-	E_PWR_READ_TEST_FAIL          = 30,
-	E_PWR_WRITE_TEST_FAIL         = 31,
-	E_PWR_SWITCH_DIO              = 32
-};
-
 #endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index ecea693f4f..7ae866cf18 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -27,47 +27,15 @@
 #define DEBUG_PMIC(level, x...)
 #endif
 
-u32 mt6391_read(u16 reg, u32 mask, u32 shift)
-{
-	u16 rdata;
-
-	pwrap_wacs2(0, reg, 0, &rdata, 1);
-	rdata &= (mask << shift);
-	rdata = (rdata >> shift);
-
-	DEBUG_PMIC(BIOS_INFO, "[%s] Reg[%#x]=%#x\n",
-		   __func__, reg, rdata);
-	return rdata;
-}
-
-void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift)
-{
-	u16 rdata;
-	u16 old_rdata, new_rdata;
-
-	pwrap_wacs2(0, reg, 0, &rdata, 1);
-	old_rdata = rdata;
-
-	rdata &= ~(mask << shift);
-	rdata |= (val << shift);
-	new_rdata = rdata;
-
-	pwrap_wacs2(1, reg, rdata, &rdata, 1);
-
-	DEBUG_PMIC(BIOS_INFO, "[%s] write Reg[%#x]=%#x -> %#x\n",
-		    __func__, reg, old_rdata, new_rdata);
-	return;
-}
-
 int mt6391_configure_ca53_voltage(int uv)
 {
 	/* target voltage = 700mv + 6.25mv * buck_val */
 	u16 buck_val = (uv - 700000) / 6250;
-	u16 current_val = mt6391_read(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
+	u16 current_val = pwrap_read_field(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
 
 	assert(buck_val < (1 << 8));
-	mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
-	mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
 
 	/* For buck delay, default slew rate is 6.25mv/0.5us */
 	if (buck_val > current_val)
@@ -83,10 +51,10 @@ static void mt6391_configure_vcama(enum ldo_voltage vsel)
 	 * 2'b10: 2.5V
 	 * 2'b11: 2.8V
 	 */
-	mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
-		     PMIC_RG_VCAMA_VOSEL_SHIFT);
-	mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
-		     PMIC_RG_VCAMA_EN_SHIFT);
+	pwrap_write_field(PMIC_RG_ANALDO_CON6, vsel - 2,
+			  PMIC_RG_VCAMA_VOSEL_MASK, PMIC_RG_VCAMA_VOSEL_SHIFT);
+	pwrap_write_field(PMIC_RG_ANALDO_CON2, 1,
+			  PMIC_RG_VCAMA_EN_MASK, PMIC_RG_VCAMA_EN_SHIFT);
 }
 
 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
@@ -122,15 +90,15 @@ void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
 	else
 		addr = PMIC_RG_DIGLDO_CON19 + ldo * 2;
 
-	mt6391_write(addr, vsel, 0x7, 5);
-	mt6391_write(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
+	pwrap_write_field(addr, vsel, 0x7, 5);
+	pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
 
 }
 
 void mt6391_enable_reset_when_ap_resets(void)
 {
 	/* Enable AP watchdog reset */
-	mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0);
+	pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0);
 }
 
 static void mt6391_init_setting(void)
@@ -141,280 +109,280 @@ static void mt6391_init_setting(void)
 	 * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1
 	 * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0
 	 */
-	mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1);
-	mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2);
-	mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4);
+	pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2);
+	pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4);
 
 	/* Disable AP watchdog reset */
-	mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0);
 
 	/* Enable CA15 by default for different PMIC behavior */
-	mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
-	mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
-	mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
 	udelay(200);  /* delay for Buck ready */
 
 	/* [3:3]: RG_PWMOC_CK_PDN; For OC protection */
-	mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);
+	pwrap_write_field(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);
 	/* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */
-	mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9);
+	pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9);
 	/* [8:8]: RG_OSC_SEL_AUTO; */
-	mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8);
 	/* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */
-	mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6);
+	pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6);
 	/* [5:5]: RG_SMPS_AUTOFF_DIS; */
-	mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5);
+	pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5);
 	/* [7:7]: VDRM_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7);
 	/* [6:6]: VSRMCA7_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6);
 	/* [5:5]: VPCA7_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5);
 	/* [4:4]: VIO18_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4);
 	/* [3:3]: VGPU_DEG_EN; For OC protection */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3);
 	/* [2:2]: VCORE_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2);
 	/* [1:1]: VSRMCA15_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1);
 	/* [0:0]: VCA15_DEG_EN; */
-	mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0);
 	/* [11:11]: RG_INT_EN_THR_H; */
-	mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 11);
+	pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 11);
 	/* [10:10]: RG_INT_EN_THR_L; */
-	mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 10);
+	pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 10);
 	/* [4:4]: RG_INT_EN_BAT_L; */
-	mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 4);
+	pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 4);
 	/* [11:11]: RG_INT_EN_VGPU; OC protection */
-	mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 11);
+	pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 11);
 	/* [8:8]: RG_INT_EN_VCA15; OC protection */
-	mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 8);
 	/* [12:0]: BUCK_RSV; for OC protection */
-	mt6391_write(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0);
+	pwrap_write_field(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0);
 	/* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */
-	mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10);
+	pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10);
 	/* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */
-	mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6);
+	pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6);
 	/* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */
-	mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4);
+	pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4);
 	/* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */
-	mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2);
+	pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2);
 	/* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */
-	mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0);
+	pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0);
 	/* [13:12]: RG_VCA15_CSL2; for OC protection */
-	mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12);
+	pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12);
 	/* [11:10]: RG_VCA15_CSL1; for OC protection */
-	mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10);
+	pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10);
 	/* [15:15]: VCA15_SFCHG_REN; soft change rising enable */
-	mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */
-	mt6391_write(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8);
 	/* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */
-	mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7);
+	pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7);
 	/* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */
-	mt6391_write(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0);
 	/* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */
-	mt6391_write(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0);
 	/* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */
-	mt6391_write(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8);
 	/* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */
-	mt6391_write(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4);
 	/* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5);
 	/* [5:4]: VSRMCA15_VOSEL_SEL; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4);
 	/* [15:15]: VSRMCA15_SFCHG_REN; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VSRMCA15_SFCHG_RRATE; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8);
 	/* [7:7]: VSRMCA15_SFCHG_FEN; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7);
 	/* [6:0]: VSRMCA15_SFCHG_FRATE; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
 	/* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */
-	mt6391_write(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
 	/* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */
-	mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
 	/* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */
-	mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
 	/* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */
-	mt6391_write(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1);
 	/* [5:4]: VCORE_VOSEL_SEL; */
-	mt6391_write(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4);
 	/* [15:15]: VCORE_SFCHG_REN; */
-	mt6391_write(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VCORE_SFCHG_RRATE; */
-	mt6391_write(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8);
 	/* [6:0]: VCORE_SFCHG_FRATE; */
-	mt6391_write(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0);
 	/* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */
-	mt6391_write(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0);
 	/* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control  R2R to */
-	mt6391_write(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8);
 	/* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */
-	mt6391_write(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4);
 	/* [1:0]: VCORE_TRANSTD; */
-	mt6391_write(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0);
+	pwrap_write_field(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0);
 	/* [9:8]: RG_VGPU_CSL; for OC protection */
-	mt6391_write(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8);
+	pwrap_write_field(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8);
 	/* [15:15]: VGPU_SFCHG_REN; */
-	mt6391_write(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VGPU_SFCHG_RRATE; */
-	mt6391_write(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8);
 	/* [6:0]: VGPU_SFCHG_FRATE; */
-	mt6391_write(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0);
 	/* [5:4]: VGPU_VOSEL_TRANS_EN; */
-	mt6391_write(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4);
 	/* [1:0]: VGPU_TRANSTD; */
-	mt6391_write(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0);
+	pwrap_write_field(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0);
 	/* [5:4]: VPCA7_VOSEL_SEL; */
-	mt6391_write(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4);
 	/* [15:15]: VPCA7_SFCHG_REN; */
-	mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VPCA7_SFCHG_RRATE; */
-	mt6391_write(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8);
 	/* [7:7]: VPCA7_SFCHG_FEN; */
-	mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7);
+	pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7);
 	/* [6:0]: VPCA7_SFCHG_FRATE; */
-	mt6391_write(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0);
 	/* [6:0]: VPCA7_VOSEL_SLEEP; */
-	mt6391_write(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0);
 	/* [8:8]: VPCA7_VSLEEP_EN; */
-	mt6391_write(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8);
 	/* [5:4]: VPCA7_VOSEL_TRANS_EN; */
-	mt6391_write(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4);
 	/* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5);
 	/* [5:4]: VSRMCA7_VOSEL_SEL; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4);
 	/* [15:15]: VSRMCA7_SFCHG_REN; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15);
 	/* [14:8]: VSRMCA7_SFCHG_RRATE; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8);
 	/* [7:7]: VSRMCA7_SFCHG_FEN; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7);
 	/* [6:0]: VSRMCA7_SFCHG_FRATE; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0);
 	/* [6:0]: VSRMCA7_VOSEL_SLEEP; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
 	/* [8:8]: VSRMCA7_VSLEEP_EN; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
 	/* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
 	/* [8:8]: VDRM_VSLEEP_EN; */
-	mt6391_write(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8);
 	/* [2:2]: VIBR_THER_SHEN_EN; */
-	mt6391_write(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2);
+	pwrap_write_field(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2);
 	/* [5:5]: THR_HWPDN_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5);
+	pwrap_write_field(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5);
 	/* [3:3]: RG_RST_DRVSEL; */
-	mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3);
+	pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3);
 	/* [2:2]: RG_EN_DRVSEL; */
-	mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2);
+	pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2);
 	/* [1:1]: PWRBB_DEB_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1);
 	/* [12:12]: VSRMCA15_PG_H2L_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12);
+	pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12);
 	/* [11:11]: VPCA15_PG_H2L_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11);
+	pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11);
 	/* [10:10]: VCORE_PG_H2L_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10);
+	pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10);
 	/* [9:9]: VSRMCA7_PG_H2L_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9);
+	pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9);
 	/* [8:8]: VPCA7_PG_H2L_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8);
 	/* [1:1]: STRUP_PWROFF_PREOFF_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1);
 	/* [0:0]: STRUP_PWROFF_SEQ_EN; */
-	mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0);
 	/* [15:8]: RG_ADC_TRIM_CH_SEL; */
-	mt6391_write(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8);
+	pwrap_write_field(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8);
 	/* [1:1]: FLASH_THER_SHDN_EN; */
-	mt6391_write(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1);
 	/* [1:1]: KPLED_THER_SHDN_EN; */
-	mt6391_write(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1);
+	pwrap_write_field(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1);
 	/* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */
-	mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8);
 	/* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */
-	mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0);
 	/* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */
-	mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8);
 	/* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */
-	mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0);
 	/* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */
-	mt6391_write(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0);
 	/* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */
-	mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8);
 	/* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */
-	mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0);
 	/* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */
-	mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8);
 	/* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */
-	mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0);
 	/* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */
-	mt6391_write(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0);
 	/* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */
-	mt6391_write(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0);
+	pwrap_write_field(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0);
 	/* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0);
 	/* [1:1]: VPCA7_VOSEL_CTRL; */
-	mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
+	pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
 	/* [1:1]: VSRMCA7_VOSEL_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
 	/* [0:0]: VSRMCA7_EN_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
 	/* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */
-	mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
+	pwrap_write_field(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
 	/* [4:4]: VSRMCA15_TRACK_ON_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4);
 	/* [4:4]: VPCA7_TRACK_ON_CTRL; */
-	mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4);
+	pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4);
 	/* [4:4]: VSRMCA7_TRACK_ON_CTRL; */
-	mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4);
 	/* [15:14]: VGPU OC; */
-	mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 14);
+	pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 14);
 	/* [3:2]: VCA15 OC; */
-	mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 2);
+	pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 2);
 
 	/* Set VPCA7 to 1.2V */
-	mt6391_write(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0);
-	mt6391_write(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0);
 	/* Set VSRMCA7 to 1.1V */
-	mt6391_write(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0);
-	mt6391_write(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0);
+	pwrap_write_field(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0);
 
 	/* Enable VGP6 and set to 3.3V*/
-	mt6391_write(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15);
-	mt6391_write(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5);
+	pwrap_write_field(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15);
+	pwrap_write_field(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5);
 
 	/* Set VDRM to 1.21875V */
-	mt6391_write(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
-	mt6391_write(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
+	pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
 
 	/* 26M clock amplitute adjust */
-	mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
-	mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
+	pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
+	pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
 
 	/* For low power, set VTCXO switch by SRCVOLTEN */
-	mt6391_write(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0);
+	pwrap_write_field(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0);
 	/* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */
-	mt6391_write(PMIC_RG_ANALDO_CON0, 0, 0x3, 13);
+	pwrap_write_field(PMIC_RG_ANALDO_CON0, 0, 0x3, 13);
 	/* [11]=0(VTCXO_ON_CTRL), */
-	mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 11);
+	pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 11);
 	/* [10]=1(RG_VTCXO_EN), */
-	mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 10);
+	pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 10);
 	/* [4:3]=1(RG_VTCXOTD_SEL) */
-	mt6391_write(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
+	pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
 	/* For low power, VIO18 set sleep_en to HW mode */
-	mt6391_write(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
+	pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
 
 }
 
 static void mt6391_default_buck_voltage(void)
 {
-	u16 reg_val = 0;
-	u16 buck_val = 0;
+	u16 reg = 0;
+	u16 buck = 0;
 	/*
 	 * There are two kinds of PMIC used for MT8173 : MT6397s/MT6391.
 	 *
@@ -427,35 +395,35 @@ static void mt6391_default_buck_voltage(void)
 	 * VPAC15/VCORE/VGPU: 1.0V
 	 * VSRMCA15: 1.0125V
 	 */
-	reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0);
+	reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0);
 
-	if ((reg_val & 0x01) == 0x01) {
+	if ((reg & 0x01) == 0x01) {
 		/* VCORE */
-		reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12);
-		buck_val = mt6391_read(PMIC_RG_VCORE_CON9, 0x7f, 0x0);
+		reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12);
+		buck = pwrap_read_field(PMIC_RG_VCORE_CON9, 0x7f, 0x0);
 
 		/* VCORE_VOSEL[3:6] => eFuse bit 268-271 */
-		buck_val = (buck_val & 0x07) | (reg_val << 3);
-		mt6391_write(PMIC_RG_VCORE_CON9, buck_val, 0x7f, 0x0);
-		mt6391_write(PMIC_RG_VCORE_CON10, buck_val, 0x7f, 0x0);
+		buck = (buck & 0x07) | (reg << 3);
+		pwrap_write_field(PMIC_RG_VCORE_CON9, buck, 0x7f, 0x0);
+		pwrap_write_field(PMIC_RG_VCORE_CON10, buck, 0x7f, 0x0);
 
-		reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0);
+		reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0);
 		/* VCA15 */
-		buck_val = 0;
-		buck_val = mt6391_read(PMIC_RG_VCA15_CON9, 0x7f, 0x0);
-		buck_val = (buck_val & 0x07) | ((reg_val & 0x0F) << 3);
-		mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
-		mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
+		buck = 0;
+		buck = pwrap_read_field(PMIC_RG_VCA15_CON9, 0x7f, 0x0);
+		buck = (buck & 0x07) | ((reg & 0x0F) << 3);
+		pwrap_write_field(PMIC_RG_VCA15_CON9, buck, 0x7f, 0x0);
+		pwrap_write_field(PMIC_RG_VCA15_CON10, buck, 0x7f, 0x0);
 
 		/* VSAMRCA15 */
-		buck_val = 0;
-		buck_val = mt6391_read(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0);
-		buck_val = (buck_val & 0x07) | ((reg_val & 0xF0) >> 1);
-		mt6391_write(PMIC_RG_VSRMCA15_CON9, buck_val, 0x7f, 0x0);
-		mt6391_write(PMIC_RG_VSRMCA15_CON10, buck_val, 0x7f, 0x0);
+		buck = 0;
+		buck = pwrap_read_field(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0);
+		buck = (buck & 0x07) | ((reg & 0xF0) >> 1);
+		pwrap_write_field(PMIC_RG_VSRMCA15_CON9, buck, 0x7f, 0x0);
+		pwrap_write_field(PMIC_RG_VSRMCA15_CON10, buck, 0x7f, 0x0);
 
 		/* set the power control by register(use original) */
-		mt6391_write(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12);
+		pwrap_write_field(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12);
 	}
 }
 
@@ -590,7 +558,7 @@ void mt6391_gpio_set_mode(u32 pin, int mode)
 	assert(pin <= MAX_MT6391_GPIO);
 
 	pos_bit_calc_mode(pin, &pos, &bit);
-	mt6391_write(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit);
+	pwrap_write_field(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit);
 }
 
 void mt6391_gpio_input_pulldown(u32 gpio)
diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c
index d7d4193c8a..2c60e76cbd 100644
--- a/src/soc/mediatek/mt8173/pmic_wrap.c
+++ b/src/soc/mediatek/mt8173/pmic_wrap.c
@@ -15,183 +15,10 @@
 
 #include <arch/io.h>
 #include <assert.h>
-#include <console/console.h>
 #include <delay.h>
 #include <soc/infracfg.h>
 #include <soc/pmic_wrap.h>
-#include <timer.h>
 
-#define PWRAPTAG                "[PWRAP] "
-#define pwrap_log(fmt, arg ...)   printk(BIOS_INFO, PWRAPTAG fmt, ## arg)
-#define pwrap_err(fmt, arg ...)   printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \
-					__LINE__, ## arg)
-
-/* define macro and inline function (for do while loop) */
-
-typedef u32 (*loop_condition_fp)(u32);
-
-static inline u32 wait_for_fsm_vldclr(u32 x)
-{
-	return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
-		WACS_FSM_WFVLDCLR;
-}
-
-static inline u32 wait_for_sync(u32 x)
-{
-	return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=
-		WACS_SYNC_IDLE;
-}
-
-static inline u32 wait_for_idle_and_sync(u32 x)
-{
-	return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
-		WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &
-		RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE));
-}
-
-static inline u32 wait_for_cipher_ready(u32 x)
-{
-	return x != 3;
-}
-
-static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,
-				      void *wacs_vldclr_register,
-				      u32 *read_reg)
-{
-	u32 reg_rdata;
-
-	struct stopwatch sw;
-
-	stopwatch_init_usecs_expire(&sw, timeout_us);
-	do {
-		reg_rdata = read32((wacs_register));
-		/* if last read command timeout,clear vldclr bit
-		   read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
-		   write:FSM_REQ-->idle */
-		switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &
-			RDATA_WACS_FSM_MASK)) {
-		case WACS_FSM_WFVLDCLR:
-			write32(wacs_vldclr_register, 1);
-			pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
-			break;
-		case WACS_FSM_WFDLE:
-			pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n");
-			break;
-		case WACS_FSM_REQ:
-			pwrap_err("WACS_FSM = WACS_FSM_REQ\n");
-			break;
-		default:
-			break;
-		}
-
-		if (stopwatch_expired(&sw))
-			return E_PWR_WAIT_IDLE_TIMEOUT;
-
-	} while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
-		 WACS_FSM_IDLE);  /* IDLE State */
-	if (read_reg)
-		*read_reg = reg_rdata;
-	return 0;
-}
-
-static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,
-				       void *wacs_register, u32 *read_reg)
-{
-	u32 reg_rdata;
-	struct stopwatch sw;
-
-	stopwatch_init_usecs_expire(&sw, timeout_us);
-	do {
-		reg_rdata = read32((wacs_register));
-
-		if (stopwatch_expired(&sw)) {
-			pwrap_err("timeout when waiting for idle\n");
-			return E_PWR_WAIT_IDLE_TIMEOUT;
-		}
-	} while (fp(reg_rdata));  /* IDLE State */
-	if (read_reg)
-		*read_reg = reg_rdata;
-	return 0;
-}
-
-s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check)
-{
-	u32 reg_rdata = 0;
-	u32 wacs_write = 0;
-	u32 wacs_adr = 0;
-	u32 wacs_cmd = 0;
-	u32 return_value = 0;
-
-	if (init_check) {
-		reg_rdata = read32(&mt8173_pwrap->wacs2_rdata);
-		/* Prevent someone to used pwrap before pwrap init */
-		if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &
-		    RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {
-			pwrap_err("initialization isn't finished\n");
-			return E_PWR_NOT_INIT_DONE;
-		}
-	}
-	reg_rdata = 0;
-	/* Check IDLE in advance */
-	return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US,
-					   &mt8173_pwrap->wacs2_rdata,
-					   &mt8173_pwrap->wacs2_vldclr,
-					   0);
-	if (return_value != 0) {
-		pwrap_err("wait_for_fsm_idle fail,return_value=%d\n",
-			  return_value);
-		return E_PWR_WAIT_IDLE_TIMEOUT;
-	}
-	wacs_write = write << 31;
-	wacs_adr = (adr >> 1) << 16;
-	wacs_cmd = wacs_write | wacs_adr | wdata;
-
-	write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd);
-	if (write == 0) {
-		if (NULL == rdata) {
-			pwrap_err("rdata is a NULL pointer\n");
-			return E_PWR_INVALID_ARG;
-		}
-		return_value = wait_for_state_ready(wait_for_fsm_vldclr,
-						    TIMEOUT_READ_US,
-						    &mt8173_pwrap->wacs2_rdata,
-						    &reg_rdata);
-		if (return_value != 0) {
-			pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n",
-				  return_value);
-			return E_PWR_WAIT_IDLE_TIMEOUT_READ;
-		}
-		*rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)
-			  & RDATA_WACS_RDATA_MASK);
-		write32(&mt8173_pwrap->wacs2_vldclr, 1);
-	}
-
-	return 0;
-}
-
-/* external API for pmic_wrap user */
-
-s32 pwrap_read(u16 adr, u16 *rdata)
-{
-	return pwrap_wacs2(0, adr, 0, rdata, 1);
-}
-
-s32 pwrap_write(u16 adr, u16 wdata)
-{
-	return pwrap_wacs2(1, adr, wdata, 0, 1);
-}
-
-static s32 pwrap_read_nochk(u16 adr, u16 *rdata)
-{
-	return pwrap_wacs2(0, adr, 0, rdata, 0);
-}
-
-static s32 pwrap_write_nochk(u16 adr, u16 wdata)
-{
-	return pwrap_wacs2(1, adr, wdata, 0, 0);
-}
-
-/* call it in pwrap_init,mustn't check init done */
 static s32 pwrap_init_dio(u32 dio_en)
 {
 	u16 rdata = 0;
@@ -203,13 +30,13 @@ static s32 pwrap_init_dio(u32 dio_en)
 	return_value =
 	wait_for_state_ready(wait_for_idle_and_sync,
 			     TIMEOUT_WAIT_IDLE_US,
-			     &mt8173_pwrap->wacs2_rdata,
+			     &mtk_pwrap->wacs2_rdata,
 			     0);
 	if (return_value != 0) {
 		pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
 		return return_value;
 	}
-	write32(&mt8173_pwrap->dio_en, dio_en);
+	write32(&mtk_pwrap->dio_en, dio_en);
 	/* Read Test */
 	pwrap_read_nochk(DEW_READ_TEST, &rdata);
 	if (rdata != DEFAULT_VALUE_READ_TEST) {
@@ -235,7 +62,7 @@ static s32 pwrap_init_sidly(void)
 	u32 sidly = 0;
 
 	for (i = 0; i < 4; i++) {
-		write32(&mt8173_pwrap->sidly, i);
+		write32(&mtk_pwrap->sidly, i);
 		pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0);
 		if (rdata == DEFAULT_VALUE_READ_TEST)
 			pass |= 1 << i;
@@ -285,49 +112,11 @@ static s32 pwrap_init_sidly(void)
 		die("sidly pass range not continuous\n");
 	}
 
-	write32(&mt8173_pwrap->sidly, sidly);
+	write32(&mtk_pwrap->sidly, sidly);
 
 	return 0;
 }
 
-static s32 pwrap_reset_spislv(void)
-{
-	u32 ret = 0;
-	u32 return_value = 0;
-
-	write32(&mt8173_pwrap->hiprio_arb_en, 0);
-	write32(&mt8173_pwrap->wrap_en, 0);
-	write32(&mt8173_pwrap->mux_sel, 1);
-	write32(&mt8173_pwrap->man_en, 1);
-	write32(&mt8173_pwrap->dio_en, 0);
-
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8));
-	/* to reset counter */
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8));
-	/*
-	 * In order to pull CSN signal to PMIC,
-	 * PMIC will count it then reset spi slave
-	*/
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
-	write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
-
-	return_value = wait_for_state_ready(wait_for_sync,
-					    TIMEOUT_WAIT_IDLE_US,
-					    &mt8173_pwrap->wacs2_rdata, 0);
-	if (return_value != 0) {
-		pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
-		ret = E_PWR_TIMEOUT;
-	}
-
-	write32(&mt8173_pwrap->man_en, 0);
-	write32(&mt8173_pwrap->mux_sel, 0);
-
-	return ret;
-}
-
 static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel)
 {
 	u16 wdata = 0;
@@ -350,25 +139,25 @@ static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel)
 	/* Config SPI Waveform according to reg clk */
 	switch (regck_sel) {
 	case REG_CLOCK_18MHZ:
-		write32(&mt8173_pwrap->rddmy, 0xc);
-		write32(&mt8173_pwrap->cshext_write, 0x0);
-		write32(&mt8173_pwrap->cshext_read, 0x4);
-		write32(&mt8173_pwrap->cslext_start, 0x0);
-		write32(&mt8173_pwrap->cslext_end, 0x4);
+		write32(&mtk_pwrap->rddmy, 0xc);
+		write32(&mtk_pwrap->cshext_write, 0x0);
+		write32(&mtk_pwrap->cshext_read, 0x4);
+		write32(&mtk_pwrap->cslext_start, 0x0);
+		write32(&mtk_pwrap->cslext_end, 0x4);
 		break;
 	case REG_CLOCK_26MHZ:
-		write32(&mt8173_pwrap->rddmy, 0xc);
-		write32(&mt8173_pwrap->cshext_write, 0x0);
-		write32(&mt8173_pwrap->cshext_read, 0x4);
-		write32(&mt8173_pwrap->cslext_start, 0x2);
-		write32(&mt8173_pwrap->cslext_end, 0x2);
+		write32(&mtk_pwrap->rddmy, 0xc);
+		write32(&mtk_pwrap->cshext_write, 0x0);
+		write32(&mtk_pwrap->cshext_read, 0x4);
+		write32(&mtk_pwrap->cslext_start, 0x2);
+		write32(&mtk_pwrap->cslext_end, 0x2);
 		break;
 	default:
-		write32(&mt8173_pwrap->rddmy, 0xf);
-		write32(&mt8173_pwrap->cshext_write, 0xf);
-		write32(&mt8173_pwrap->cshext_read, 0xf);
-		write32(&mt8173_pwrap->cslext_start, 0xf);
-		write32(&mt8173_pwrap->cslext_end, 0xf);
+		write32(&mtk_pwrap->rddmy, 0xf);
+		write32(&mtk_pwrap->cshext_write, 0xf);
+		write32(&mtk_pwrap->cshext_read, 0xf);
+		write32(&mtk_pwrap->cslext_start, 0xf);
+		write32(&mtk_pwrap->cslext_end, 0xf);
 		break;
 	}
 
@@ -388,8 +177,8 @@ s32 pwrap_init(void)
 	clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
 
 	/* Enable DCM */
-	write32(&mt8173_pwrap->dcm_en, 3);
-	write32(&mt8173_pwrap->dcm_dbc_prd, 0);
+	write32(&mtk_pwrap->dcm_en, 3);
+	write32(&mtk_pwrap->dcm_dbc_prd, 0);
 
 	/* Reset SPISLV */
 	sub_return = pwrap_reset_spislv();
@@ -399,9 +188,9 @@ s32 pwrap_init(void)
 		return E_PWR_INIT_RESET_SPI;
 	}
 	/* Enable WACS2 */
-	write32(&mt8173_pwrap->wrap_en, 1);
-	write32(&mt8173_pwrap->hiprio_arb_en, WACS2);
-	write32(&mt8173_pwrap->wacs2_en, 1);
+	write32(&mtk_pwrap->wrap_en, 1);
+	write32(&mtk_pwrap->hiprio_arb_en, WACS2);
+	write32(&mtk_pwrap->wacs2_en, 1);
 
 	/* SIDLY setting */
 	sub_return = pwrap_init_sidly();
@@ -461,14 +250,14 @@ s32 pwrap_init(void)
 		pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return);
 		return E_PWR_INIT_ENABLE_CRC;
 	}
-	write32(&mt8173_pwrap->crc_en, 0x1);
-	write32(&mt8173_pwrap->sig_mode, 0x0);
-	write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL);
+	write32(&mtk_pwrap->crc_en, 0x1);
+	write32(&mtk_pwrap->sig_mode, 0x0);
+	write32(&mtk_pwrap->sig_adr, DEW_CRC_VAL);
 
 	/* PMIC_WRAP enables */
-	write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff);
-	write32(&mt8173_pwrap->wacs0_en, 0x1);
-	write32(&mt8173_pwrap->wacs1_en, 0x1);
+	write32(&mtk_pwrap->hiprio_arb_en, 0x1ff);
+	write32(&mtk_pwrap->wacs0_en, 0x1);
+	write32(&mtk_pwrap->wacs1_en, 0x1);
 
 	/*
 	 * switch event pin from usbdl mode to normal mode for pmic interrupt,
@@ -481,9 +270,9 @@ s32 pwrap_init(void)
 			  sub_return);
 
 	/* Initialization Done */
-	write32(&mt8173_pwrap->init_done2, 0x1);
-	write32(&mt8173_pwrap->init_done0, 0x1);
-	write32(&mt8173_pwrap->init_done1, 0x1);
+	write32(&mtk_pwrap->init_done2, 0x1);
+	write32(&mtk_pwrap->init_done0, 0x1);
+	write32(&mtk_pwrap->init_done1, 0x1);
 
 	return 0;
 }
diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 4d2cad42b9..153e9b4249 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -102,7 +102,7 @@ static void rtc_xosc_write(u16 val)
 
 	pwrap_write(RTC_OSC32CON, val);
 	udelay(200);
-	mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+	pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
 	write_trigger();
 }
 
@@ -175,15 +175,15 @@ static void rtc_osc_init(void)
 /* low power detect setting */
 static int rtc_lpd_init(void)
 {
-	mt6391_write(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
+	pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
 	if (!write_trigger())
 		return 0;
 
-	mt6391_write(RTC_CON, RTC_CON_LPRST, 0, 0);
+	pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
 	if (!write_trigger())
 		return 0;
 
-	mt6391_write(RTC_CON, 0, RTC_CON_LPRST, 0);
+	pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
 	if (!write_trigger())
 		return 0;
 
@@ -203,7 +203,7 @@ static int rtc_init(u8 recover)
 
 	/* Use SW to detect 32K mode instead of HW */
 	if (recover)
-		mt6391_write(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
+		pwrap_write_field(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
 
 	rtc_xosc_write(0x3);
 
@@ -217,7 +217,7 @@ static int rtc_init(u8 recover)
 		return 0;
 
 	if (recover)
-		mt6391_write(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
+		pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
 
 	rtc_xosc_write(0);
 
@@ -243,17 +243,17 @@ static void rtc_bbpu_power_on(void)
 
 	/* enable DCXO to transform external 32KHz clock to 26MHz clock
 	   directly sent to SoC */
-	mt6391_write(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
-	mt6391_write(PMIC_RG_DCXO_POR2_CON3,
+	pwrap_write_field(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
+	pwrap_write_field(PMIC_RG_DCXO_POR2_CON3,
 		     BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
-	mt6391_write(PMIC_RG_DCXO_CON2,
+	pwrap_write_field(PMIC_RG_DCXO_CON2,
 		     BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
 
 	pwrap_read(RTC_BBPU, &bbpu);
 	printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
 
 	/* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
-	mt6391_write(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
+	pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
 }
 
 static u8 rtc_check_state(void)
@@ -293,7 +293,8 @@ void rtc_boot(void)
 
 	switch (rtc_check_state()) {
 	case RTC_STATE_REBOOT:
-		mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+		pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0,
+				  0);
 		write_trigger();
 		rtc_osc_init();
 		break;