diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:43:30 +0200 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-09-10 06:37:52 +0000 |
| commit | 1a8b50089d9434aeb49668f780810cde8030fc5d (patch) | |
| tree | 61529b5267a16ba23f2ab193bf0236dd80ed37de /src/soc/mediatek/mt8173 | |
| parent | f8f8615eef5898c8dcb32a21338b9bfa5b2da5eb (diff) | |
soc/mediatek: Drop unneeded empty lines
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/mediatek/mt8173')
| -rw-r--r-- | src/soc/mediatek/mt8173/da9212.c | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/mt6311.c | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/pll.c | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/rtc.c | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index 8c98b35f7f..e44a76f592 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -56,7 +56,6 @@ void da9212_probe(uint8_t i2c_num) unsigned char device_id = 0; unsigned char variant_id = 0; - /* select to page 4, clear REVERT at first time */ ret |= i2c_write_field(i2c_num, DA9212_SLAVE_ADDR, DA9212_REG_PAGE_CON, DA9212_REG_PAGE4, diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index e8fe6dc6d3..3e61f8c399 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -25,7 +25,6 @@ static void mt6311_hw_init(uint8_t i2c_num) int ret = 0; unsigned char var[3] = {0}; - /* * Phase Shedding Trim Software Setting * The phase 2 of MT6311 will enter PWM mode if the threshold is diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 8a86f0b3ae..0fe94cf0c3 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -373,7 +373,6 @@ void mt_pll_enable_ssusb_clk(void) setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } - /* after pmic_init */ void mt_pll_post_init(void) { diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index ef57fa6204..d08de45325 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -9,7 +9,6 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc related gpio */ static int rtc_gpio_init(void) { |