diff options
author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-06-19 15:28:55 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-08 11:58:42 +0000 |
commit | 86b3bf10e60c137b01b81a37ce9827757f6af42d (patch) | |
tree | ea5e759fc4615a2629fac4c85503510c77b63cd0 /src/soc/mediatek/mt8173 | |
parent | 83b33f62cf7b125b524b2fbdea5bd8317be0c154 (diff) |
soc/mediatek: Add function to raise the CPU frequency of MT8192
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8173')
-rw-r--r-- | src/soc/mediatek/mt8173/pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 0fe94cf0c3..7133fde400 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -417,7 +417,7 @@ void mt_pll_set_aud_div(u32 rate) } } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } |