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authorWisley <wisley.chen@quantatw.com>2015-11-24 20:12:36 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-12-03 14:23:21 +0100
commit1a8e43e4e3e081e8e6c9037bbef4a7a18a181309 (patch)
treeef2a00cb1e392abfd9d3f19ff00aed4a146695d0 /src/soc/mediatek/mt8173
parent8c83c65ef3a5346c30c88c8d7d088be6b84c6756 (diff)
google/chell: update dptf TSR1 & TSR2 critial points
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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