mediatek/mt8183: Fix RTC initialization flow

1. Fix RTC lpd settings. Rewrite powerkeys after lpd init
   to enable low power detect function.
2. Rearrange RTC initialization flow.
3. Add return status for rtc_init.
4. Add log if calling pwrap_write or pwrap_read fail.
5. Increase timeout time to resolve unexpected timeout.

BUG=b:127405695
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

1 files changed, 50 insertions, 28 deletions

diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 5b7d486d87..ca81d26bb0 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -30,11 +30,11 @@ static int rtc_gpio_init(void)
 				MT6391_GPIO_PULL_DOWN);  /* RTC_32K1V8 */
 
 	/* Export 32K clock RTC_32K2V8 */
-	pwrap_read(RTC_CON, &con);
+	rtc_read(RTC_CON, &con);
 	con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN);
 	con |= (RTC_CON_GPEN | RTC_CON_GOE);
 	con &= ~(RTC_CON_F32KOB);
-	pwrap_write(RTC_CON, con);
+	rtc_write(RTC_CON, con);
 	return rtc_write_trigger();
 }
 
@@ -46,8 +46,8 @@ void rtc_osc_init(void)
 	/* enable 32K export */
 	rtc_gpio_init();
 
-	pwrap_write(PMIC_RG_TOP_CKTST2, 0x0);
-	pwrap_read(RTC_OSC32CON, &con);
+	rtc_write(PMIC_RG_TOP_CKTST2, 0x0);
+	rtc_read(RTC_OSC32CON, &con);
 	if ((con & 0x1f) != 0x0)	/* check XOSCCALI */
 		rtc_xosc_write(0x3);
 }
@@ -73,40 +73,62 @@ static int rtc_lpd_init(void)
 /* rtc init check */
 int rtc_init(u8 recover)
 {
-	printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
+	int ret;
 
-	if (!rtc_writeif_unlock())
-		return 0;
+	rtc_info("recovery: %d\n", recover);
 
-	if (!rtc_gpio_init())
-		return 0;
+	if (!rtc_writeif_unlock()) {
+		ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
+		goto err;
+	}
+
+	if (!rtc_gpio_init()) {
+		ret = -RTC_STATUS_GPIO_INIT_FAIL;
+		goto err;
+	}
 
 	/* Use SW to detect 32K mode instead of HW */
 	if (recover)
 		pwrap_write_field(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
 
-	rtc_xosc_write(0x3);
+	if (!rtc_xosc_write(0x3)) {
+		ret = -RTC_STATUS_OSC_SETTING_FAIL;
+		goto err;
+	}
 
 	if (recover)
 		mdelay(1000);
 
 	/* write powerkeys */
-	pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
-	pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
-	if (!rtc_write_trigger())
-		return 0;
+	rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
+	rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
+	if (!rtc_write_trigger()) {
+		ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
+		goto err;
+	}
 
 	if (recover)
 		pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
 
-	rtc_xosc_write(0);
-
-	if (!rtc_reg_init())
-		return 0;
-	if (!rtc_lpd_init())
-		return 0;
-
-	return 1;
+	if (!rtc_xosc_write(0)) {
+		ret = -RTC_STATUS_OSC_SETTING_FAIL;
+		goto err;
+	}
+
+	if (!rtc_reg_init()) {
+		ret = -RTC_STATUS_REG_INIT_FAIL;
+		goto err;
+	}
+
+	if (!rtc_lpd_init()) {
+		ret = -RTC_STATUS_LPD_INIT_FAIL;
+		goto err;
+	}
+
+	return RTC_STATUS_OK;
+err:
+	rtc_info("init fail: ret=%d\n", ret);
+	return ret;
 }
 
 /* enable rtc bbpu */
@@ -117,9 +139,9 @@ static void rtc_bbpu_power_on(void)
 
 	/* pull PWRBB high */
 	bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
-	pwrap_write(RTC_BBPU, bbpu);
+	rtc_write(RTC_BBPU, bbpu);
 	ret = rtc_write_trigger();
-	printk(BIOS_INFO, "[RTC] %s rtc_write_trigger=%d\n", __func__, ret);
+	rtc_info("rtc_write_trigger=%d\n", ret);
 
 	/* enable DCXO to transform external 32KHz clock to 26MHz clock
 	   directly sent to SoC */
@@ -129,8 +151,8 @@ static void rtc_bbpu_power_on(void)
 	pwrap_write_field(PMIC_RG_DCXO_CON2,
 		     BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
 
-	pwrap_read(RTC_BBPU, &bbpu);
-	printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_info("done BBPU=%#x\n", bbpu);
 
 	/* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
 	pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
@@ -139,8 +161,8 @@ static void rtc_bbpu_power_on(void)
 /* the rtc boot flow entry */
 void rtc_boot(void)
 {
-	pwrap_write(PMIC_RG_TOP_CKPDN, 0);
-	pwrap_write(PMIC_RG_TOP_CKPDN2, 0);
+	rtc_write(PMIC_RG_TOP_CKPDN, 0);
+	rtc_write(PMIC_RG_TOP_CKPDN2, 0);
 
 	rtc_boot_common();
 	rtc_bbpu_power_on();