diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-06-06 12:52:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-07 07:42:43 +0000 |
| commit | f42db110d0174f05745e3558067d114eae37825b (patch) | |
| tree | a5a52a630e8704369f57d6d21077e95c13733cb7 /src/soc/mediatek/mt8173/pll.c | |
| parent | 794284ff0ee92f7f60c4d33dbf43bf007979389c (diff) | |
mediatek: Refine whitespace and formating changes
This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8173/pll.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/pll.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 1366bb5888..d95f769c9f 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -328,7 +328,7 @@ void mt_pll_init(void) for (i = 0; i < APMIXED_NR_PLL; i++) setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); - udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ + udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ /****************** * xPLL ISO Disable @@ -361,7 +361,7 @@ void mt_pll_init(void) for (i = 0; i < APMIXED_NR_PLL; i++) setbits_le32(plls[i].reg, PLL_EN); - udelay(40); /* wait for PLL stable (min delay is 20us) */ + udelay(40); /* wait for PLL stable (min delay is 20us) */ /*************** * xPLL DIV RSTB @@ -448,12 +448,12 @@ void mt_pll_enable_ssusb_clk(void) { /* set RG_LTECLKSQ_EN */ setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1); - udelay(100); /* wait for PLL stable */ + udelay(100); /* wait for PLL stable */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1); setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1); - udelay(100); /* wait for PLL stable */ + udelay(100); /* wait for PLL stable */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); |