diff options
author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-07-16 20:16:40 +0800 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2018-07-27 05:34:58 +0000 |
commit | 86d0d6e2cf83b73403823c69792a3ddfe1b00fde (patch) | |
tree | e8b623410b0eb2ec03198ade776559067d3bba11 /src/soc/mediatek/mt8173/include | |
parent | 9d6523c7db74da39cbe787d3af9bdff21ebc986c (diff) |
mediatek: Refactor SPI code among similar SOCs
Refactor SPI code which will be reused amon similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
-rw-r--r-- | src/soc/mediatek/mt8173/include/soc/spi.h | 69 |
1 files changed, 3 insertions, 66 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 52f4f4cef3..aaef3aa25c 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -16,8 +16,9 @@ #ifndef MTK_MT8173_SPI_H #define MTK_MT8173_SPI_H -#include <spi-generic.h> -#include <types.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 1 /* SPI peripheral register map. */ typedef struct mtk_spi_regs { @@ -35,7 +36,6 @@ typedef struct mtk_spi_regs { check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); -/* SPI_CFG0_REG */ enum { SPI_CFG0_SCK_HIGH_SHIFT = 0, SPI_CFG0_SCK_LOW_SHIFT = 8, @@ -43,67 +43,4 @@ enum { SPI_CFG0_CS_SETUP_SHIFT = 24, }; -/*SPI_CFG1_REG*/ -enum { - SPI_CFG1_CS_IDLE_SHIFT = 0, - SPI_CFG1_PACKET_LOOP_SHIFT = 8, - SPI_CFG1_PACKET_LENGTH_SHIFT = 16, - - SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, - SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, - SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, -}; - -enum { - SPI_CMD_ACT_SHIFT = 0, - SPI_CMD_RESUME_SHIFT = 1, - SPI_CMD_RST_SHIFT = 2, - SPI_CMD_PAUSE_EN_SHIFT = 4, - SPI_CMD_DEASSERT_SHIFT = 5, - SPI_CMD_CPHA_SHIFT = 8, - SPI_CMD_CPOL_SHIFT = 9, - SPI_CMD_RX_DMA_SHIFT = 10, - SPI_CMD_TX_DMA_SHIFT = 11, - SPI_CMD_TXMSBF_SHIFT = 12, - SPI_CMD_RXMSBF_SHIFT = 13, - SPI_CMD_RX_ENDIAN_SHIFT = 14, - SPI_CMD_TX_ENDIAN_SHIFT = 15, - SPI_CMD_FINISH_IE_SHIFT = 16, - SPI_CMD_PAUSE_IE_SHIFT = 17, - - SPI_CMD_ACT_EN = BIT(SPI_CMD_ACT_SHIFT), - SPI_CMD_RESUME_EN = BIT(SPI_CMD_RESUME_SHIFT), - SPI_CMD_RST_EN = BIT(SPI_CMD_RST_SHIFT), - SPI_CMD_PAUSE_EN = BIT(SPI_CMD_PAUSE_EN_SHIFT), - SPI_CMD_DEASSERT_EN = BIT(SPI_CMD_DEASSERT_SHIFT), - SPI_CMD_CPHA_EN = BIT(SPI_CMD_CPHA_SHIFT), - SPI_CMD_CPOL_EN = BIT(SPI_CMD_CPOL_SHIFT), - SPI_CMD_RX_DMA_EN = BIT(SPI_CMD_RX_DMA_SHIFT), - SPI_CMD_TX_DMA_EN = BIT(SPI_CMD_TX_DMA_SHIFT), - SPI_CMD_TXMSBF_EN = BIT(SPI_CMD_TXMSBF_SHIFT), - SPI_CMD_RXMSBF_EN = BIT(SPI_CMD_RXMSBF_SHIFT), - SPI_CMD_RX_ENDIAN_EN = BIT(SPI_CMD_RX_ENDIAN_SHIFT), - SPI_CMD_TX_ENDIAN_EN = BIT(SPI_CMD_TX_ENDIAN_SHIFT), - SPI_CMD_FINISH_IE_EN = BIT(SPI_CMD_FINISH_IE_SHIFT), - SPI_CMD_PAUSE_IE_EN = BIT(SPI_CMD_PAUSE_IE_SHIFT), -}; - -enum spi_pad_mask { - SPI_PAD0_MASK = 0x0, - SPI_PAD1_MASK = 0x1, - SPI_PAD2_MASK = 0x2, - SPI_PAD3_MASK = 0x3, - SPI_PAD_SEL_MASK = 0x3 -}; - - -struct mtk_spi_bus { - struct spi_slave slave; - struct mtk_spi_regs *regs; - int initialized; - int state; -}; - -void mtk_spi_init(unsigned int bus, unsigned int pad_select, - unsigned int speed_hz); #endif |