diff options
| author | Daniel Kurtz <djkurtz@chromium.org> | 2017-04-18 21:13:30 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-04-24 22:32:52 +0200 |
| commit | 50340f5480c943b6434c9b5e6178731a9977cae3 (patch) | |
| tree | e42965d633f28200cd08aed407aa8d8a37198a01 /src/soc/mediatek/mt8173/include | |
| parent | 732618975ee688059ca50f87a76f8a3bed8d4fb1 (diff) | |
mediatek/mt8173: Add EINT support
Add basic support to configure GPIOs to poll for external interrupts
(EINT).
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/gpio.h | 51 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 00c9a6e49c..cab127be75 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -34,6 +34,7 @@ enum { SPM_BASE = IO_PHYS + 0x6000, RGU_BASE = IO_PHYS + 0x7000, GPT_BASE = IO_PHYS + 0x8000, + EINT_BASE = IO_PHYS + 0xB000, PMIC_WRAP_BASE = IO_PHYS + 0xD000, CHA_DDRPHY_BASE = IO_PHYS + 0xF000, CHB_DRAMCAO_BASE = IO_PHYS + 0x11000, diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index 3968d04f94..1c05e48b14 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -87,4 +87,55 @@ void gpio_set_pull(gpio_t gpio, enum pull_enable enable, void gpio_set_mode(gpio_t gpio, int mode); void gpio_init(enum external_power); +enum gpio_irq_type { + IRQ_TYPE_EDGE_RISING, + IRQ_TYPE_EDGE_FALLING, + IRQ_TYPE_LEVEL_HIGH, + IRQ_TYPE_LEVEL_LOW, +}; + +struct eint_section { + uint32_t regs[7]; + uint32_t align1[9]; +}; + +struct eint_regs { + struct eint_section sta; + struct eint_section ack; + struct eint_section mask; + struct eint_section mask_set; + struct eint_section mask_clr; + struct eint_section sens; + struct eint_section sens_set; + struct eint_section sens_clr; + struct eint_section soft; + struct eint_section soft_set; + struct eint_section soft_clr; + struct eint_section rsv00; + struct eint_section pol; + struct eint_section pol_set; + struct eint_section pol_clr; + struct eint_section rsv01; + uint32_t d0en[7]; + uint32_t rsv02; + uint32_t d1en[7]; +}; + +check_member(eint_regs, d1en, 0x420); + +static struct eint_regs *const mt8173_eint = (void *)(EINT_BASE); + +/* + * Firmware never enables interrupts on this platform. This function + * reads current EINT status and clears the pending interrupt. + * + * Returns 1 if the interrupt was pending, else 0. + */ +int gpio_eint_poll(gpio_t gpio); + +/* + * Configure a GPIO to handle external interrupts (EINT) of given irq type. + */ +void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type); + #endif /* SOC_MEDIATEK_MT8173_GPIO_H */ |