diff options
| author | PH Hsu <ph.hsu@mediatek.com> | 2016-05-17 08:47:56 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:13:10 +0200 |
| commit | cf6526c21135f81acca43d1fcc4566d7c1a86681 (patch) | |
| tree | ca6be877a5fd72fc50b86d29a2479bc81b67b748 /src/soc/mediatek/mt8173/dramc_pi_basic_api.c | |
| parent | 99f065fb6eddd46f829a756704a954d60ea201c6 (diff) | |
mt8173: dram: Add more sample points to improve dram timing margin
BRANCH=none
BUG=chrome-os-partner:52959
TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models.
Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3c19e7d
Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347716
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15115
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8173/dramc_pi_basic_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index ac28373a39..e3efec9cf8 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -539,8 +539,11 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ao_regs->conf1, sdram_params->ac_timing.conf1); + /* bit 17,18 would bypass some dummy path */ write32(&ch[channel].ddrphy_regs->dqsgctl, 0x1 << 31 | 0x1 << 30 | + 0x1 << 17 | + 0x1 << 18 | 0x1 << 4 | 0x1 << 0); @@ -691,6 +694,9 @@ void dramc_phy_reset(u32 channel) void dramc_runtime_config(u32 channel, const struct mt8173_sdram_params *sdram_params) { + setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + BIT(17)|BIT(18)); + /* enable hw gating */ setbits_le32(&ch[channel].ao_regs->dqscal0, 1 << DQSCAL0_STBCALEN_SHIFT); |