soc/mediatek/mt8173: Remove dual DSI mode

The 'dual DSI mode' was never used by any real boards running coreboot
and is introducing lots of complexity when it comes to refactoring.

In order to create a common display stack for MTK SOCs, we want to first
drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more
similar to each other.

BUG=b:80501386,b:117254947
TEST=emerge-oak coreboot

Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 51 deletions

diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c
index f8896d391a..d3d91ef96e 100644
--- a/src/soc/mediatek/mt8173/ddp.c
+++ b/src/soc/mediatek/mt8173/ddp.c
@@ -24,22 +24,13 @@
 #define RDMA_FIFO_PSEUDO_SIZE(bytes)            (((bytes) / 16) << 16)
 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
 
-static void disp_config_main_path_connection(bool dual_dsi_mode)
+static void disp_config_main_path_connection(void)
 {
 	write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0);
-
 	write32(&mmsys_cfg->disp_color0_sel_in, COLOR0_SEL_IN_OVL0);
-
 	write32(&mmsys_cfg->disp_od_mout_en, OD_MOUT_EN_RDMA0);
-
-	if (dual_dsi_mode) {
-		write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_SPLIT1);
-		write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_SPLIT1);
-		write32(&mmsys_cfg->dsi1_sel_in, DSI1_SEL_IN_SPLIT1);
-	} else {
-		write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0);
-		write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE);
-	}
+	write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0);
+	write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE);
 }
 
 static void disp_config_main_path_mutex(void)
@@ -105,15 +96,9 @@ static void od_start(u32 width, u32 height)
 	write32(&disp_od->en, 1);
 }
 
-static void ufoe_start(u32 width, u32 height, bool dual_dsi_mode)
+static void ufoe_start(u32 width, u32 height)
 {
-	if (dual_dsi_mode) {
-		write32(&disp_ufoe->frame_width, width);
-		write32(&disp_ufoe->frame_height, height);
-		write32(&disp_ufoe->start, UFO_LR);
-	} else {
-		write32(&disp_ufoe->start, UFO_BYPASS);
-	}
+	write32(&disp_ufoe->start, UFO_BYPASS);
 }
 
 static void color_start(u32 width, u32 height)
@@ -124,11 +109,6 @@ static void color_start(u32 width, u32 height)
 	write32(&disp_color[0]->start, BIT(0));
 }
 
-static void split_start(void)
-{
-	write32(&disp_split->start, 1);
-}
-
 static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
 {
 	write32(&disp_ovl[0]->layer[0].con, fmt << 12);
@@ -138,8 +118,7 @@ static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
 	ovl_layer_enable();
 }
 
-static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk,
-				 bool dual_dsi_mode)
+static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk)
 {
 	/* Setup OVL */
 	ovl_set_roi(width, height, 0);
@@ -151,34 +130,20 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk,
 	od_start(width, height);
 
 	/* Setup UFOE */
-	ufoe_start(width, height, dual_dsi_mode);
-
-	if (dual_dsi_mode)
-		split_start();
+	ufoe_start(width, height);
 
 	/* Setup Color */
 	color_start(width, height);
 
 	/* Setup main path connection */
-	disp_config_main_path_connection(dual_dsi_mode);
+	disp_config_main_path_connection();
 
 	/* Setup main path mutex */
 	disp_config_main_path_mutex();
 }
 
-static void disp_clock_on(bool dual_dsi_mode)
+static void disp_clock_on(void)
 {
-	u32 dual_dsi_cg_con0;
-	u32 dual_dsi_cg_con1;
-
-	if (dual_dsi_mode) {
-		dual_dsi_cg_con0 = CG_CON0_DISP_SPLIT1;
-		dual_dsi_cg_con1 = CG_CON1_DSI1_ENGINE | CG_CON1_DSI1_DIGITAL;
-	} else {
-		dual_dsi_cg_con0 = 0;
-		dual_dsi_cg_con1 = 0;
-	}
-
 	clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON |
 						CG_CON0_SMI_LARB0 |
 						CG_CON0_MUTEX_32K |
@@ -186,26 +151,24 @@ static void disp_clock_on(bool dual_dsi_mode)
 						CG_CON0_DISP_RDMA0 |
 						CG_CON0_DISP_COLOR0 |
 						CG_CON0_DISP_UFOE |
-						dual_dsi_cg_con0 |
 						CG_CON0_DISP_OD);
 
 	clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE |
-						CG_CON1_DSI0_DIGITAL |
-						dual_dsi_cg_con1);
+						CG_CON1_DSI0_DIGITAL);
 }
 
-void mtk_ddp_init(bool dual_dsi_mode)
+void mtk_ddp_init(void)
 {
-	disp_clock_on(dual_dsi_mode);
+	disp_clock_on();
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode)
+void mtk_ddp_mode_set(const struct edid *edid)
 {
 	u32 fmt = OVL_INFMT_RGBA8888;
 	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
 
 	main_disp_path_setup(edid->mode.ha, edid->mode.va,
-			     edid->mode.pixel_clock, dual_dsi_mode);
+			     edid->mode.pixel_clock);
 
 	rdma_start();