mediatek: Share MMU operation code among similar SOCs

Refactor MMU operation code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

2 files changed, 103 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h
new file mode 100644
index 0000000000..b081690451
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/mmu_operations.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__
+#define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__
+
+#include <arch/mmu.h>
+
+enum {
+	DEV_MEM		= MA_DEV | MA_S  | MA_RW,
+	CACHED_MEM	= MA_MEM | MA_NS | MA_RW,
+	SECURE_MEM	= MA_MEM | MA_S  | MA_RW,
+	UNCACHED_MEM	= MA_MEM | MA_NS | MA_RW | MA_MEM_NC,
+};
+
+extern unsigned char _sram_l2c[];
+extern unsigned char _esram_l2c[];
+#define _sram_l2c_size (_esram_l2c - _sram_l2c)
+
+void mtk_soc_after_dram(void);
+void mtk_soc_disable_l2c_sram(void);
+
+void mtk_mmu_init(void);
+void mtk_mmu_after_dram(void);
+void mtk_mmu_disable_l2c_sram(void);
+
+#endif
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
new file mode 100644
index 0000000000..b9910845c1
--- /dev/null
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/mmu.h>
+#include <compiler.h>
+#include <symbols.h>
+#include <soc/emi.h>
+#include <soc/mmu_operations.h>
+
+__weak void mtk_soc_after_dram(void) { /* do nothing */ }
+
+void mtk_mmu_init(void)
+{
+	mmu_init();
+
+	/* Set 0x0 to the end of 2GB dram address as device memory */
+	mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);
+
+	/* SRAM is cached */
+	mmu_config_range(_sram, _sram_size, CACHED_MEM);
+
+	/* L2C SRAM is cached */
+	mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);
+
+	/* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
+	mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
+
+	mmu_enable();
+}
+
+void mtk_mmu_after_dram(void)
+{
+	/* Map DRAM as cached now that it's up and running */
+	mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
+
+	mtk_soc_after_dram();
+}
+
+void mtk_mmu_disable_l2c_sram(void)
+{
+	/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
+	/* TODO: Implement true unmapping, and also use it for the zero-page! */
+	mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
+
+	/* Careful: changing cache geometry while it's active is a bad idea! */
+	mmu_disable();
+
+	mtk_soc_disable_l2c_sram();
+
+	/* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
+	mmu_enable();
+}