diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-05-13 10:01:14 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-12 02:51:39 +0000 |
| commit | a4cad368a2996645d2ffc71425f49b246b0340ad (patch) | |
| tree | b8cc9dd452fcdb4235d6bbaf49a12977f633aa7b /src/soc/mediatek/common | |
| parent | 8fcc246a565b0d687c2891396719e677fe9bdf23 (diff) | |
soc/mediatek/mt8192: Add PLL and clock init support
Add PLL and clock init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pll_common.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/common/pll.c | 12 |
2 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 681b97c5e3..a1bd96d4aa 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -20,6 +20,8 @@ struct mux { void *reg; + void *set_reg; + void *clr_reg; void *upd_reg; u8 mux_shift; u8 mux_width; diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 35b03d845e..539d82cafe 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel) u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); + if (mux->set_reg && mux->clr_reg) { + write32(mux->clr_reg, mask << mux->mux_shift); + write32(mux->set_reg, sel << mux->mux_shift); + } else { + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + } + if (mux->upd_reg) write32(mux->upd_reg, 1 << mux->upd_shift); } |