soc/mediatek: Refactor MMU operation for L2C SRAM and DMA

Refactor mmu operation by
- moving mtk_soc_disable_l2c_sram to l2c_ops.c
- keeping mtk_soc_after_dram in mmu_cmops.c

Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 31 insertions, 28 deletions

diff --git a/src/soc/mediatek/common/l2c_ops.c b/src/soc/mediatek/common/l2c_ops.c
new file mode 100644
index 0000000000..f748ab02cd
--- /dev/null
+++ b/src/soc/mediatek/common/l2c_ops.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}
diff --git a/src/soc/mediatek/common/mmu_cmops.c b/src/soc/mediatek/common/mmu_cmops.c
index 4b81a276b6..e102569745 100644
--- a/src/soc/mediatek/common/mmu_cmops.c
+++ b/src/soc/mediatek/common/mmu_cmops.c
@@ -1,34 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/mmio.h>
-#include <soc/mcucfg.h>
-#include <soc/mmu_operations.h>
 #include <soc/symbols.h>
-
-DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
-DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
-
-void mtk_soc_disable_l2c_sram(void)
-{
-	unsigned long v;
-
-	SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
-			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
-	dsb();
-
-	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
-	v |= (0xf << 4);
-	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
-	dsb();
-
-	do {
-		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
-	} while (((v >> 0x4) & 0xf) != 0xf);
-
-	SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
-			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
-	dsb();
-}
+#include <soc/mmu_operations.h>
 
 /* mtk_soc_after_dram is called in romstage */
 void mtk_soc_after_dram(void)