diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-09-27 13:06:53 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-03 18:51:24 +0000 |
| commit | a23d76a8bcaff5fedc370a9850d953005f261202 (patch) | |
| tree | a1152ffdad79f94ef14cddcf84d7f12f501ccddb /src/soc/mediatek/common | |
| parent | 9559c68b3cf24780d351875a007fb5c57303c3a6 (diff) | |
soc/mediatek: Add an overridable function for WDT clear status
mtk_wdt_clr_status is different for MT8186 and MT8195,
so we move this function to soc folder.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/wdt.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 5 |
3 files changed, 4 insertions, 8 deletions
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 754c0da580..b581ffb85f 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -29,11 +29,6 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. -config CLEAR_WDT_MODE_REG - bool - help - Enable this option to clear WTD mode register explicitly. - config DPM_FOUR_CHANNEL bool default n diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 5847d4953f..6b27beffc3 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,7 +21,6 @@ struct mtk_wdt_regs { /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, - MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, @@ -40,5 +39,6 @@ enum { static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; int mtk_wdt_init(void); +void mtk_wdt_clr_status(uint32_t wdt_sta); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 05bd27d277..b228e56a05 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -5,6 +5,8 @@ #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> +__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ } + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -12,8 +14,7 @@ int mtk_wdt_init(void) /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); - if (CONFIG(CLEAR_WDT_MODE_REG)) - write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + mtk_wdt_clr_status(wdt_sta); printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { |