soc/mediatek/mt8195: Add timer support

TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
     verified on Asurada and Cherry P0

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 98 insertions, 44 deletions

diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h
deleted file mode 100644
index 1ebee8f04e..0000000000
--- a/src/soc/mediatek/common/include/soc/timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_COMMON_TIMER_H
-#define SOC_MEDIATEK_COMMON_TIMER_H
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define GPT_MHZ	13
-
-struct mtk_gpt_regs {
-	u32 reserved1[24];
-	u32 gpt6_con;
-	u32 gpt6_clk;
-	u32 gpt6_cnt_l;
-	u32 reserved2[3];
-	u32 gpt6_cnt_h;
-};
-
-check_member(mtk_gpt_regs, gpt6_con, 0x0060);
-check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
-check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
-check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
-
-enum {
-	GPT_CON_EN        = 0x01,
-	GPT_CON_CLR       = 0x02,
-	GPT_MODE_FREERUN  = 0x30,
-	GPT_SYS_CLK       = 0x00,
-	GPT_CLK_DIV1      = 0x00,
-};
-
-/*
- * This is defined as weak no-ops that can be overridden by legacy SOCs. Some
- * legacy SOCs need specific settings before init timer. And we expect future
- * SOCs will not need it.
- */
-void timer_prepare(void);
-
-#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_common.h b/src/soc/mediatek/common/include/soc/timer_common.h
new file mode 100644
index 0000000000..40d150b3f6
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_common.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_COMMON_H
+#define SOC_MEDIATEK_COMMON_TIMER_COMMON_H
+
+#include <types.h>
+
+enum {
+	GPT6_CON_EN		= BIT(0),
+	GPT6_CON_CLR		= BIT(1),
+	GPT6_MODE_FREERUN	= 3,
+	GPT6_CLK_CLK6_SYS	= 0,
+	GPT6_CLK_CLKDIV_DIV1	= 0,
+};
+
+/*
+ * This is defined as weak no-ops that can be overridden by legacy SOCs. Some
+ * legacy SOCs need specific settings before init timer. And we expect future
+ * SOCs will not need it.
+ */
+void timer_prepare(void);
+
+#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_v1.h b/src/soc/mediatek/common/include/soc/timer_v1.h
new file mode 100644
index 0000000000..8d64b5d163
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_v1.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_V1_H
+#define SOC_MEDIATEK_COMMON_TIMER_V1_H
+
+#include <device/mmio.h>
+#include <soc/timer_common.h>
+#include <types.h>
+
+#define GPT_MHZ	13
+
+struct mtk_gpt_regs {
+	u32 reserved1[24];
+	u32 gpt6_con;
+	u32 gpt6_clk;
+	u32 gpt6_cnt_l;
+	u32 reserved2[3];
+	u32 gpt6_cnt_h;
+};
+
+check_member(mtk_gpt_regs, gpt6_con, 0x0060);
+check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
+
+DEFINE_BIT(GPT6_CON_EN6, 0)
+DEFINE_BIT(GPT6_CON_CLR6, 1)
+DEFINE_BITFIELD(GPT6_CON_MODE6, 5, 4)
+
+#define GPT6_CLOCK_REG(x) x->gpt6_clk
+DEFINE_BITFIELD(GPT6_CLK_CLKDIV6, 3, 0)
+DEFINE_BIT(GPT6_CLK_CLK6, 4)
+
+#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h
new file mode 100644
index 0000000000..507814b233
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_v2.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_V2_H
+#define SOC_MEDIATEK_COMMON_TIMER_V2_H
+
+#include <device/mmio.h>
+#include <soc/timer_common.h>
+#include <types.h>
+
+#define GPT_MHZ	13
+
+struct mtk_gpt_regs {
+	u32 reserved1[40];
+	u32 gpt6_con;
+	u32 reserved2;
+	u32 gpt6_cnt_l;
+	u32 reserved3;
+	u32 gpt6_cnt_h;
+};
+
+check_member(mtk_gpt_regs, gpt6_con, 0x00A0);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x00A8);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x00B0);
+
+DEFINE_BIT(GPT6_CON_EN6, 0)
+DEFINE_BIT(GPT6_CON_CLR6, 1)
+DEFINE_BITFIELD(GPT6_CON_MODE6, 6, 5)
+
+#define GPT6_CLOCK_REG(x) x->gpt6_con
+DEFINE_BITFIELD(GPT6_CLK_CLKDIV6, 3, 0)
+DEFINE_BITFIELD(GPT6_CLK_CLK6, 13, 10)
+
+#endif
diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c
index 7b9e424153..5feed3420b 100644
--- a/src/soc/mediatek/common/timer.c
+++ b/src/soc/mediatek/common/timer.c
@@ -35,11 +35,15 @@ void init_timer(void)
 	timer_prepare();
 
 	/* Disable timer and clear the counter */
-	clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN);
-	setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
+	clrbits32(&mtk_gpt->gpt6_con, GPT6_CON_EN);
+	setbits32(&mtk_gpt->gpt6_con, GPT6_CON_CLR);
 
 	/* Set clock source to system clock and set clock divider to 1 */
-	write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
+	SET32_BITFIELDS(&GPT6_CLOCK_REG(mtk_gpt),
+			GPT6_CLK_CLK6, GPT6_CLK_CLK6_SYS,
+			GPT6_CLK_CLKDIV6, GPT6_CLK_CLKDIV_DIV1);
 	/* Set operation mode to FREERUN mode and enable timer */
-	write32(&mtk_gpt->gpt6_con, GPT_CON_EN | GPT_MODE_FREERUN);
+	SET32_BITFIELDS(&mtk_gpt->gpt6_con,
+			GPT6_CON_MODE6, GPT6_MODE_FREERUN,
+			GPT6_CON_EN6, GPT6_CON_EN);
 }