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authorFelix Held <felix-coreboot@felixheld.de>2020-12-12 22:28:54 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-13 22:20:13 +0000
commit9ef72ca7db807a7ae2e7d78144773940dd688a78 (patch)
treebd23edddb89d3e33a61380484bdd0ed2af049c87 /src/soc/mediatek/common
parent815efe16cb6916334866084c921431a5be4157df (diff)
mb/google/kahlee: move SMI/SCI GPIO setup to ramstage
SMIs and SCIs aren't used before ramstage or the OS, so there should be no need to already set them up in romstage. Not using this GPIO configuration functionality allows untangling the GPIO and smi_util code and only linking smi_util in ramstage in follow-up patches. In romstage the pins get initialized as inputs with pull-up, so that at least that part still matches the configuration before this patch. BUG=b:175386410 Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/mediatek/common')
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