diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2019-08-07 10:58:36 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-08-15 00:51:05 +0000 |
| commit | 32ddc0d9f7186471c2f1ae8dc7279639dcaadb06 (patch) | |
| tree | 7e4a73e02cdac26010f001b2c9c52e96c113142e /src/soc/mediatek/common | |
| parent | 75e4314675cecf6faf7c02920a86f3157e6ba5c1 (diff) | |
soc/mediatek/mt8183: Add DSI driver
The MT8183 display serial interface (DSI) is based on MIPI
Alliance Specification, supporting high-speed serial data
transfer between host processor and peripheral devices such
as display modules.
DSI supports both video mode and command mode data transfer
defined in MIPI spec, and it also provides bidirectional
transmission with low-power mode to receive messages from
the peripheral.
Reference: MT8183 Application Processor Functional Spec,
6.7 Display Serial Interface (DSI)
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/dsi.c | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/dsi_common.h | 23 |
2 files changed, 27 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index fffe51f708..166bc17eee 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -248,6 +248,12 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, write32(&dsi0->dsi_psctrl, PIXEL_STREAM_CUSTOM_HEADER << DSI_PSCON_CUSTOM_HEADER_SHIFT | packet_fmt); + + /* Older systems like MT8173 do not support size_con. */ + if (MTK_DSI_HAVE_SIZE_CON) + write32(&dsi0->dsi_size_con, + edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT | + hactive << DSI_SIZE_CON_WIDTH_SHIFT); } static void mtk_dsi_start(void) diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 3f4a47d1b8..c684aaf940 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -67,7 +67,11 @@ struct dsi_regs { u32 dsi_vbp_nl; u32 dsi_vfp_nl; u32 dsi_vact_nl; - u8 reserved1[32]; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; u32 dsi_hsa_wc; u32 dsi_hbp_wc; u32 dsi_hfp_wc; @@ -84,7 +88,9 @@ struct dsi_regs { u32 dsi_phy_timecon3; u8 reserved4[16]; u32 dsi_vm_cmd_con; - u8 reserved5[204]; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[108]; u32 dsi_cmdq[128]; }; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; @@ -92,6 +98,7 @@ static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; check_member(dsi_regs, dsi_phy_lccon, 0x104); check_member(dsi_regs, dsi_phy_timecon3, 0x11c); check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); check_member(dsi_regs, dsi_cmdq, 0x200); /* DSI_INTSTA */ @@ -134,6 +141,12 @@ enum { DSI_PSCON_CUSTOM_HEADER_SHIFT = 26, }; +/* DSI_SIZE_CON */ +enum { + DSI_SIZE_CON_HEIGHT_SHIFT = 16, + DSI_SIZE_CON_WIDTH_SHIFT = 0, +}; + /* DSI_CMDQ_SIZE */ enum { CMDQ_SIZE = 0x3f, @@ -196,6 +209,12 @@ enum { DATA_1 = (0xff << 24), }; +/* DSI_FORCE_COMMIT */ +enum { + DSI_FORCE_COMMIT_USE_MMSYS = BIT(0), + DSI_FORCE_COMMIT_ALWAYS = BIT(1), +}; + /* MIPI DSI Processor-to-Peripheral transaction types */ enum { MIPI_DSI_V_SYNC_START = 0x01, |