Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c
index c8af2be113..6fc2ab2fe9 100644
--- a/src/soc/mediatek/common/timer.c
+++ b/src/soc/mediatek/common/timer.c
@@ -48,8 +48,8 @@ void init_timer(void)
 	timer_prepare();
 
 	/* Disable timer and clear the counter */
-	clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN);
-	setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
+	clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN);
+	setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
 
 	/* Set clock source to system clock and set clock divider to 1 */
 	write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);