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authorShuo Liu <shuo.liu@intel.com>2024-04-26 06:15:35 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-05-02 17:43:51 +0000
commit45a670d223ce7e77a4ba1e5d6419753d2e6a558d (patch)
tree9c588cca7797e926bfdf05167261031f0391fa9b /src/soc/mediatek/common/reset.c
parenta0aff6e15988f918b926c4cd222537d2f5a3f878 (diff)
soc/intel/xeon_sp: Move VPD based settings to mainboard codes
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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