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authorJianjun Wang <jianjun.wang@mediatek.com>2022-03-14 20:38:18 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-03-16 16:55:26 +0000
commitc0808b64978056e72514525733e290b495cc0777 (patch)
tree6e2b3524085e84450e445adb108d1f6aa03d484c /src/soc/mediatek/common/include
parentd59b3dd08540b7cf42dc98d68da42b2a4305f6ee (diff)
soc/mediatek: Add chip config for setting PCIe config
Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common/include')
-rw-r--r--src/soc/mediatek/common/include/soc/pcie_common.h8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h
index d737c9dd9b..0f02ab7a90 100644
--- a/src/soc/mediatek/common/include/soc/pcie_common.h
+++ b/src/soc/mediatek/common/include/soc/pcie_common.h
@@ -13,12 +13,10 @@ struct mtk_pcie_mmio_res {
unsigned long type;
};
-struct mtk_pcie_controller {
+struct mtk_pcie_config {
uintptr_t base; /* MAC physical address */
- int (*phy_init)(void);
- void (*reset)(uintptr_t base, bool enable);
- const struct mtk_pcie_mmio_res *mmio_res_io;
- const struct mtk_pcie_mmio_res *mmio_res_mem;
+ const struct mtk_pcie_mmio_res mmio_res_io;
+ const struct mtk_pcie_mmio_res mmio_res_mem;
};
void mtk_pcie_domain_read_resources(struct device *dev);