soc/mediatek: Use MRC cache API for asurada

Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.

This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.

Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.

With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none

Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

2 files changed, 7 insertions, 14 deletions

diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/common/include/soc/dramc_param.h
index d3eda8da92..e809379261 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param.h
@@ -3,21 +3,21 @@
 #ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__
 #define __SOC_MEDIATEK_DRAMC_PARAM_H__
 
-/* any change in this file should sync to blob dramc_param.h */
+/*
+ * This file is shared between coreboot and dram blob. Any change in this file
+ * should be synced to the other repository.
+ */
 
 #include <stdint.h>
 #include <sys/types.h>
 #include <soc/dramc_soc.h>
 
-enum {
-	DRAMC_PARAM_HEADER_VERSION = 5,
-};
+#define DRAMC_PARAM_HEADER_VERSION 6
 
 enum DRAMC_PARAM_STATUS_CODES {
 	DRAMC_SUCCESS = 0,
 	DRAMC_ERR_INVALID_VERSION,
 	DRAMC_ERR_INVALID_SIZE,
-	DRAMC_ERR_INVALID_CHECKSUM,
 	DRAMC_ERR_INVALID_FLAGS,
 	DRAMC_ERR_RECALIBRATE,
 	DRAMC_ERR_INIT_DRAM,
@@ -41,7 +41,6 @@ enum DRAMC_PARAM_DDR_TYPE {
 	DDR_TYPE_EMCP,
 };
 
-/* Don't change the order, which is matched with blob */
 enum DRAMC_PARAM_GEOMETRY_TYPE {
 	DDR_TYPE_2CH_2RK_4GB_2_2,
 	DDR_TYPE_2CH_2RK_6GB_3_3,
@@ -58,7 +57,6 @@ enum DRAM_PARAM_VOLTAGE_TYPE {
 };
 
 struct dramc_param_header {
-	u32 checksum;	/* checksum of dramc_datas, update in the coreboot */
 	u16 version;	/* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */
 	u16 size;	/* size of whole dramc_param, update in the coreboot */
 	u16 status;	/* DRAMC_PARAM_STATUS_CODES, update in the dram blob */
@@ -141,12 +139,6 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param_ops {
-	struct dramc_param *param;
-	bool (*read_from_flash)(struct dramc_param *dparam);
-	bool (*write_to_flash)(const struct dramc_param *dparam);
-};
-
 struct sdram_info {
 	u32 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
 	u32 ddr_type;			/* DRAMC_PARAM_DDR_TYPE */
diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h
index c91c8706c4..994d35a8ec 100644
--- a/src/soc/mediatek/common/include/soc/emi.h
+++ b/src/soc/mediatek/common/include/soc/emi.h
@@ -7,7 +7,8 @@
 
 size_t sdram_size(void);
 void mt_set_emi(struct dramc_param *dparam);
-void mt_mem_init(struct dramc_param_ops *dparam_ops);
+void mt_mem_init(struct dramc_param *dparam);
+void mtk_dram_init(void);
 int complex_mem_test(u8 *start, unsigned int len);
 
 bool is_dvfs_enabled(void);