soc/mediatek: dsi: Refactor PHY timing calculation

The PHY timing should be calculated by data rate (Mbps). However for
8173 some values were hard-coded so we want to introduce a new
mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing
that allows per-SOC customization to apply PHY timings.

BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots

Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 7241097380..bfdd4073d6 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -300,10 +300,33 @@ enum {
 	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
 };
 
+struct mtk_phy_timing {
+	u8 lpx;
+	u8 da_hs_prepare;
+	u8 da_hs_zero;
+	u8 da_hs_trail;
+
+	u8 ta_go;
+	u8 ta_sure;
+	u8 ta_get;
+	u8 da_hs_exit;
+
+	u8 da_hs_sync;
+	u8 clk_hs_zero;
+	u8 clk_hs_trail;
+
+	u8 clk_hs_prepare;
+	u8 clk_hs_post;
+	u8 clk_hs_exit;
+};
+
 /* Functions that each SOC should provide. */
 void mtk_dsi_reset(void);
 void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes);
 
+/* Functions as weak no-ops that can be overridden. */
+void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
+
 /* Public API provided in common/dsi.c */
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes,
 		 const struct edid *edid);