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authorTristan Shieh <tristan.shieh@mediatek.com>2019-04-08 11:01:40 +0800
committerJulius Werner <jwerner@chromium.org>2019-04-17 04:32:26 +0000
commita76e6542d1ab39ca50777f3fd0146151d0868c5c (patch)
tree8011717f7cf8ef7e826825caa8f7bdfcdd0ea853 /src/soc/mediatek/common/include
parent250dfc025613f5e193183f9520432207f4b296e4 (diff)
mediatek: Use the 64-bit timer
GPT4 is a 32-bit timer and the counter of GPT4 will overflow in about 330 seconds (0xffffffff / 13MHz). Timer and delay functions will not work properly if the counter overflows. To fix that we should use the 64-bit timer (GPT6). BUG=b:80501386 BRANCH=none Test=emerge-elm coreboot; emerge-kukui coreboot Change-Id: I9f080e47253a1b1bab4636a45cb86c8666a25302 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
Diffstat (limited to 'src/soc/mediatek/common/include')
-rw-r--r--src/soc/mediatek/common/include/soc/timer.h19
1 files changed, 11 insertions, 8 deletions
diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h
index babcbba561..b58d4d3227 100644
--- a/src/soc/mediatek/common/include/soc/timer.h
+++ b/src/soc/mediatek/common/include/soc/timer.h
@@ -19,18 +19,21 @@
#include <soc/addressmap.h>
#include <types.h>
-#define GPT4_MHZ 13
+#define GPT_MHZ 13
struct mtk_gpt_regs {
- u32 reserved[16];
- u32 gpt4_con;
- u32 gpt4_clk;
- u32 gpt4_cnt;
+ u32 reserved1[24];
+ u32 gpt6_con;
+ u32 gpt6_clk;
+ u32 gpt6_cnt_l;
+ u32 reserved2[3];
+ u32 gpt6_cnt_h;
};
-check_member(mtk_gpt_regs, gpt4_con, 0x0040);
-check_member(mtk_gpt_regs, gpt4_clk, 0x0044);
-check_member(mtk_gpt_regs, gpt4_cnt, 0x0048);
+check_member(mtk_gpt_regs, gpt6_con, 0x0060);
+check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
enum {
GPT_CON_EN = 0x01,