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| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-07-23 15:04:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 09:21:39 +0000 |
| commit | 8dfeb06eb139889a7bb71284897811cd37ce3d89 (patch) | |
| tree | 407475fd1f849b57a28b899f4d4253c295e31c4a /src/soc/mediatek/common/include | |
| parent | e9fed766df9ebc6b9e0806d42be9a343f26f5011 (diff) | |
soc/mediatek/mt8192: Add function to raise the CCI frequency
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Usage: mt_pll_raise_cci_freq(1400UL * MHz);
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common/include')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pll_common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index ae6ad64ded..cb22796ebf 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -69,6 +69,7 @@ void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +void mt_pll_raise_cci_freq(u32 freq); enum fmeter_type { FMETER_ABIST = 0, |