soc/mediatek/mt8196: Add version two DPM driver

Add version two of the DPM driver for DVFS and DRAM low power feature.

MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we implement a new DPM loader (said version 2) to run the
blob. The new DPM driver includes following features.
- Simplify the DPM loading flow without the needs of waking DPM SRAM up
  and initializing bootargs.
- Use the broadcast function to ensure that the DPM load and reset
  operations performed on channel A will be synchronized to the other
  three channels.

TEST=Full calibration pass.
BUG=b:317009620

Change-Id: I77e1ac252b00ab9c4864cc308f20da4a79714e4c
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85121
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

1 files changed, 22 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/include/soc/dpm_v2.h b/src/soc/mediatek/common/include/soc/dpm_v2.h
new file mode 100644
index 0000000000..c11a9bb2da
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dpm_v2.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_DPM_V2_H__
+#define __SOC_MEDIATEK_COMMON_DPM_V2_H__
+
+#include <soc/addressmap.h>
+#include <soc/mcu_common.h>
+
+#define DPM_RST_OFFSET		0x7074
+#define DPM_SW_RSTN		BIT(0)
+
+#define DPM_CFG_CH0		DPM_CFG_BASE
+#define DPM_BARGS_CH0_REG0	(DPM_CFG_BASE + 0x6004)
+#define DPM_BARGS_CH0_REG1	(DPM_CFG_BASE + 0x6008)
+#define DRAMC_WBR		(INFRACFG_AO_BASE + 0x0b4)
+
+#define ENABLE_DRAMC_WBR_MASK	0x2ffff
+
+void dpm_reset(struct mtk_mcu *mcu);
+int dpm_init(void);
+
+#endif  /* __SOC_MEDIATEK_COMMON_DPM_V2_H__ */