diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-07-14 15:38:19 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2022-03-09 00:48:01 +0000 |
| commit | 270b0b60acba4802b8a9272d2727ee576733ad47 (patch) | |
| tree | aa3d78475995894890f9e9208c82efd0a96f8a6b /src/soc/mediatek/common/include | |
| parent | f53214677caca8077d83fbde3d351a2899cdae16 (diff) | |
soc/mediatek: Add PCIe support
Add PCIe support for MediaTek platform.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
- linux/drivers/pci/controller/pcie-mediatek-gen3.c
This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common/include')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pcie_common.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h new file mode 100644 index 0000000000..d737c9dd9b --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_PCIE_COMMON_H +#define SOC_MEDIATEK_PCIE_COMMON_H + +#include <device/device.h> +#include <types.h> + +struct mtk_pcie_mmio_res { + uint32_t cpu_addr; + uint32_t pci_addr; + uint32_t size; + unsigned long type; +}; + +struct mtk_pcie_controller { + uintptr_t base; /* MAC physical address */ + int (*phy_init)(void); + void (*reset)(uintptr_t base, bool enable); + const struct mtk_pcie_mmio_res *mmio_res_io; + const struct mtk_pcie_mmio_res *mmio_res_mem; +}; + +void mtk_pcie_domain_read_resources(struct device *dev); +void mtk_pcie_domain_set_resources(struct device *dev); +void mtk_pcie_domain_enable(struct device *dev); + +#endif |