mediatek: Refactor I2C code among similar SOCs

Refactor I2C code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot

Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c
Signed-off-by: qii wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 99 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h
new file mode 100644
index 0000000000..c9dade4d82
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/i2c_common.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MTK_COMMON_I2C_H
+#define MTK_COMMON_I2C_H
+
+/* I2C DMA Registers */
+struct mt_i2c_dma_regs {
+	uint32_t dma_int_flag;
+	uint32_t dma_int_en;
+	uint32_t dma_en;
+	uint32_t dma_rst;
+	uint32_t reserved1;
+	uint32_t dma_flush;
+	uint32_t dma_con;
+	uint32_t dma_tx_mem_addr;
+	uint32_t dma_rx_mem_addr;
+	uint32_t dma_tx_len;
+	uint32_t dma_rx_len;
+};
+
+check_member(mt_i2c_dma_regs, dma_tx_len, 0x24);
+
+/* I2C Configuration */
+enum {
+	I2C_HS_DEFAULT_VALUE	 = 0x0102,
+};
+
+enum i2c_modes {
+	I2C_WRITE_MODE		= 0,
+	I2C_READ_MODE		= 1,
+	I2C_WRITE_READ_MODE	= 2,
+};
+
+enum {
+	I2C_DMA_CON_TX          = 0x0,
+	I2C_DMA_CON_RX          = 0x1,
+	I2C_DMA_START_EN        = 0x1,
+	I2C_DMA_INT_FLAG_NONE   = 0x0,
+	I2C_DMA_CLR_FLAG        = 0x0,
+	I2C_DMA_FLUSH_FLAG      = 0x1,
+};
+
+enum {
+	I2C_TRANS_LEN_MASK = (0xff),
+	I2C_TRANS_AUX_LEN_MASK = (0x1f << 8),
+	I2C_CONTROL_MASK = (0x3f << 1)
+};
+
+/* Register mask */
+enum {
+	I2C_HS_NACKERR = (1 << 2),
+	I2C_ACKERR = (1 << 1),
+	I2C_TRANSAC_COMP = (1 << 0),
+};
+
+/* i2c control bits */
+enum {
+	ASYNC_MODE = (1 << 9),
+	DMAACK_EN = (1 << 8),
+	ACK_ERR_DET_EN = (1 << 5),
+	DIR_CHG = (1 << 4),
+	CLK_EXT = (1 << 3),
+	DMA_EN = (1 << 2),
+	REPEATED_START_FLAG = (1 << 1),
+	STOP_FLAG = (0 << 1)
+};
+
+/* I2C Status Code */
+
+enum {
+	I2C_OK = 0x0000,
+	I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001,
+	I2C_TRANSFER_INVALID_LENGTH = 0xA002,
+	I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003,
+	I2C_TRANSFER_FAIL_ACKERR = 0xA004,
+	I2C_TRANSFER_FAIL_TIMEOUT = 0xA005,
+	I2C_TRANSFER_INVALID_ARGUMENT = 0xA006
+};
+
+struct mtk_i2c {
+	struct mt_i2c_regs *i2c_regs;
+	struct mt_i2c_dma_regs *i2c_dma_regs;
+};
+
+extern struct mtk_i2c mtk_i2c_bus_controller[];
+#endif