soc/mediatek/common: Refactor EINT driver

Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
  `gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.

This change is prepared for the driver change in MT8196.

BUG=b:334723688
TEST=EINT works on Geralt

Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 12 deletions

diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c
index e8a50b2b18..bbfbb3d175 100644
--- a/src/soc/mediatek/common/gpio.c
+++ b/src/soc/mediatek/common/gpio.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <device/mmio.h>
 #include <gpio.h>
 
@@ -113,23 +114,16 @@ void gpio_output(gpio_t gpio, int value)
 	gpio_set_mode(gpio, GPIO_MODE);
 }
 
-enum {
-	MAX_EINT_REG_BITS = 32,
-};
-
-static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit)
-{
-	*pos = gpio.id / MAX_EINT_REG_BITS;
-	*bit = gpio.id % MAX_EINT_REG_BITS;
-}
-
 int gpio_eint_poll(gpio_t gpio)
 {
 	u32 pos;
 	u32 bit;
 	u32 status;
+	struct eint_regs *mtk_eint;
 
-	pos_bit_calc_for_eint(gpio, &pos, &bit);
+	gpio_calc_eint_pos_bit(gpio, &pos, &bit);
+	mtk_eint = gpio_get_eint_reg(gpio);
+	assert(mtk_eint);
 
 	status = (read32(&mtk_eint->sta.regs[pos]) >> bit) & 0x1;
 
@@ -143,8 +137,12 @@ void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
 {
 	u32 pos;
 	u32 bit, mask;
+	struct eint_regs *mtk_eint;
+
+	gpio_calc_eint_pos_bit(gpio, &pos, &bit);
+	mtk_eint = gpio_get_eint_reg(gpio);
+	assert(mtk_eint);
 
-	pos_bit_calc_for_eint(gpio, &pos, &bit);
 	mask = 1 << bit;
 
 	/* Make it an input first. */