Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c
index 173fa90cd7..8f1f0e64ac 100644
--- a/src/soc/mediatek/common/ddp.c
+++ b/src/soc/mediatek/common/ddp.c
@@ -31,7 +31,7 @@ void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
 
 void rdma_start(void)
 {
-	setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
+	setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
 }
 
 void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
@@ -39,8 +39,8 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
 	u32 threshold;
 	u32 reg;
 
-	clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width);
-	clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height);
+	clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width);
+	clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height);
 
 	/*
 	 * Enable FIFO underflow since DSI and DPI can't be blocked. Set the
@@ -78,5 +78,5 @@ void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
 	write32(&ovl0->rdma[0].ctrl, BIT(0));
 	write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
 
-	setbits_le32(&ovl0->src_con, BIT(0));
+	setbits32(&ovl0->src_con, BIT(0));
 }