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authorSubrata Banik <subrata.banik@intel.com>2017-08-30 18:29:33 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-09-01 02:55:45 +0000
commita281c0f1bf7b6b84c4e1f7739c52044299ae0be5 (patch)
treef1c7467908bdab3da7fd1f945f3790b9fc726746 /src/soc/marvell/mvmap2315/Makefile.inc
parentce90c78d7f27e41275deb36b5dea2787ffced8bf (diff)
soc/intel/cannonlake: Perform dram top calculation based on HW registers
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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