diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-02-03 18:57:49 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-14 19:13:03 +0100 |
| commit | a4b11e5c90a51dadc9b02ec080c0fb192cac3997 (patch) | |
| tree | 6770d18fbf8dfb9dbd0e85fffdc062b30bfd404d /src/soc/marvell/bg4cd/spi.c | |
| parent | 408fda799a55c4d104178dfa733b4ade2ad454cf (diff) | |
soc/intel/skylake: Perform CPU MP Init before FSP-S Init
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/marvell/bg4cd/spi.c')
0 files changed, 0 insertions, 0 deletions