diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2021-12-16 17:46:33 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-07 15:27:31 +0000 |
| commit | ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (patch) | |
| tree | a2d1668ecff1cc5db153fa255d8828613d060cee /src/soc/intel | |
| parent | 328bfb39373357114166e65f84e96a726afceb45 (diff) | |
soc/intel/alderlake: Check clkreq overlap
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message
TEST=On brya, assigned one clkreq to 2 devices and found the warning
message
Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 0eeaabde69..790aa99bb9 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -47,14 +47,21 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ const struct pcie_rp_config *cfg, size_t cfg_count) { size_t i; + /* bitmask to save the status of clkreq assignment */ + static unsigned int clk_req_mapping = 0; for (i = 0; i < cfg_count; i++) { if (!(en_mask & BIT(i))) continue; if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) continue; - if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" + , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + clk_req_mapping |= 1 << cfg[i].clk_req; + } m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); } } |