diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2022-01-25 19:48:38 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-28 15:09:23 +0000 |
| commit | f711bf03a694bc594a610a70251716d425fbe101 (patch) | |
| tree | 52312b90ce5da720335815cfb51438b34bb45441 /src/soc/intel | |
| parent | f9e9250d46a15d61036279dc5b6276510db83fc9 (diff) | |
soc/intel/common/cse: skip heci_init() if HECI1 is disabled
If the HECI1 PCI device is disabled, either via devicetree or other
method (HAP, me_cleaner), then we don't want/need to program a BAR,
set the PCI config, or call heci_reset(), as the latter will result
in a 15s timeout delay when booting.
Test: build/boot Purism Librem 13v2, verify heci_reset()
timeout delay is no longer present.
Change-Id: I0babe417173d10e37327538dc9e7aae980225367
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7d6fabaa9b..32f6d4f0c2 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -94,6 +94,10 @@ void heci_init(uintptr_t tempbar) u16 pcireg; + /* Check if device enabled */ + if (!is_cse_enabled()) + return; + /* Assume it is already initialized, nothing else to do */ if (get_cse_bar(dev)) return; |