diff options
| author | Martin Roth <martin@coreboot.org> | 2020-07-24 12:24:27 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:20:30 +0000 |
| commit | f48acbda7be7074938c06db8ad37705f850661ee (patch) | |
| tree | 4e06af0923d793db47700aae5a5b3f374c8529d8 /src/soc/intel | |
| parent | af56a7791565de4c3dec66b4cc6a8b152bba014c (diff) | |
src: Change BOOL CONFIG_ to CONFIG() in comments & strings
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/systemagent.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_def.h | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index ef55699df3..5edfaeecaf 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 72d611a2cc..e12e07c376 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -226,7 +226,7 @@ static void imr_resource(struct device *dev, int idx, uint32_t base, /* * Add IMR ranges that hang off the host bridge/memory - * controller device in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * controller device in case CONFIG(SA_ENABLE_IMR) is selected by SoC. */ static void sa_add_imr_resources(struct device *dev, int *resource_cnt) { diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index a7823c347c..149e9b6ace 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -40,7 +40,7 @@ #define MCH_PAIR 0x5418 /* - * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC. * * IMR registers are found under MCHBAR. */ |