diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-11 10:28:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-13 14:29:40 +0000 |
| commit | f12c2b0837f9dfdf70e04a87215695f6d859f719 (patch) | |
| tree | 4375ea2635edf7d9fff21b9df163ca15e7ce91d4 /src/soc/intel | |
| parent | b988f8aac542adebcde13d7d90e5def414a3c972 (diff) | |
soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 878b2a689c..a7b63db036 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -133,9 +133,9 @@ void soc_clear_pm_registers(uintptr_t pmc_bar) { uint32_t gen_pmcon1; - gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); + gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) @@ -157,10 +157,10 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); - ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); - ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); - ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); + ps->prsts = read32p(pmc_bar0 + PRSTS); + ps->gen_pmcon1 = read32p(pmc_bar0 + GEN_PMCON1); + ps->gen_pmcon2 = read32p(pmc_bar0 + GEN_PMCON2); + ps->gen_pmcon3 = read32p(pmc_bar0 + GEN_PMCON3); printk(BIOS_DEBUG, "prsts: %08x\n", ps->prsts); @@ -200,7 +200,7 @@ int soc_get_rtc_failed(void) int vbnv_cmos_failed(void) { uintptr_t pmc_bar = soc_read_pmc_base(); - uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); + uint32_t gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1); int rtc_failure = rtc_failed(gen_pmcon1); if (rtc_failure) { @@ -212,7 +212,7 @@ int vbnv_cmos_failed(void) /* RPS is write 0 to clear. */ gen_pmcon1 &= ~RPS; - write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1); + write32p(pmc_bar + GEN_PMCON1, gen_pmcon1); } return rtc_failure; |